System for fast posting to shared queues in multi-processor environments utilizing interrupt state checking
AssigneeLSI Logic Corporation
InventorsStephen C. Hagan, Keith W. Holt
Life of this patent
Estimating the term…
Abstract
A method and apparatus for efficiently posting entries to a queue within the data processing system. Entries are posted by first processor with the entries being handled by second processor in the data processing system. The interrupt state associated with the queue is checked by the first processor. If the interrupt state is clear, then the entry is posted to the queue. This interrupt state is cleared only when all entries have been cleared from the queue by the second processor. In this manner, an efficient posting of entries to the queue may be accomplished.
Claims34
A method for posting entries to a queue in a data processing system, wherein entries are posted by first processor and handled by second processor, the method comprising:
- checking an interrupt state associated with the queue, wherein the interrupt state being set indicates a posting of an entry to the queue;
- and
- posting an entry to the queue in response to a determination that the interrupt state is clear, wherein the interrupt state is cleared in response to all entries being cleared from the queue, providing for an efficient posting of entries to the queue.
A data processing system comprising:
- a first processor, wherein the first processor posts entries to a queue;
- a second processor, wherein the second processor handles entries posted to the queue by the first processor;
- checking means, responsive to a presence of an entry for checking an interrupt state associated with the queue, wherein the interrupt state being set indicates a posting of an entry to the queue;
- and
- writing means, responsive to a determination that the interrupt state is clear, for writing the entry to the queue, wherein the interrupt state is cleared when entries have been cleared from the queue.
A data processing system comprising:
- a memory;
- a queue located in the memory, the queue having a plurality of elements for storing entries;
- an interrupt state associated with the queue, wherein the interrupt state being set indicates a posting of an entry to the queue;
- a first processor, the first processor for reading entries in the queue, wherein the first processor clears the interrupt state in response to reading all entries within the queue;
- a second processor, the second processor having a plurality of modes of operation including:
- a first mode of operation, responsive to an entry being present for the queue, in which the interrupt state associated with the queue is checked;
- and
- a second mode of operation, responsive to a determination that the interrupt state is clear, in which an entry is posted to the queue.
Computer program product comprising a computer readable media having computer readable instructions embodied therein for posting entries to a queue, wherein the computer readable instructions include:
- first instructions for checking an interrupt state associated with the queue, wherein the interrupt state indicates a posting of an entry to the queue;
- and
- second instructions for posting an entry to the queue in response to a determination that the interrupt state is clear, wherein the interrupt state is cleared when all entries have been cleared from the queue.
Dependencies are inferred from the claim text.