Data speculatable processor having reply architecture
AssigneeIntel Corporation
InventorDavid J. Sager
Life of this patent
Estimating the term…
Abstract
A microprocessor having a replay architecture with an execution core for performing data speculation in executing an instruction, a delay unit for making a copy of the instruction and holding the copy for as long as the instruction takes to execute, and a checker for determining whether the data speculation was bogus. If the data speculation was bogus, the delay unit and its buffer send the copy of the instruction back to the execution core for re-execution. A multiplexor coupled to the input of the execution core selects for execution among original instructions from the instruction cache, replay instructions from the delay unit, and manufactured instructions from various other units such as the TLB or tag units, according to a priority scheme.
Claims13
A microprocessor having a replay architecture and comprising:
- an execution core for performing data speculation in executing a first instruction;
- a delay unit for making a copy of the first instruction and for holding that copy for at least one clock cycle;
- a checker, coupled to the execution core, for determining whether the data speculation was erroneous, and coupled to the delay unit for sending the copy of the first instruction back to the execution core for re-execution if the data speculation was erroneous;
- an instruction cache for storing and providing the first instruction and a subsequent instruction;
- and
- a multiplexor, coupled to the instruction cache to receive the first instruction and the subsequent instruction, and coupled to the checker to receive the copy of the first instruction, and coupled to an input of the execution core to selectively provide either the subsequent instruction or the copy of the first instruction to the execution core for execution.
A processor comprising:
- a first section operating at a first clock frequency and including,
- an execution core;
- a plurality of registers;
- and
- a second section operating at a second clock frequency lower than the first clock frequency and including,
- a checker for determining whether an instruction was processed correctly and used input data that are known to be correct, the checker comprising,
- a scoreboard for keeping track of which of the registers have contents which are known to be correct,
- a delay line, coupled to receive a latency vector indicating how many clock cycles after a first instruction begins execution can a second instruction use a result of the first instruction, and
- logic circuitry, coupled to the scoreboard and to the delay line, for indicating whether the instruction was correctly completed or the instruction needs to be replayed.
A microprocessor comprising:
- an instruction cache for storing original instructions;
- a renamer, coupled to the instruction cache, for modifying the original instructions to rename registers identified in the original instructions;
- a scheduler, coupled to the renamer, for dispatching instructions for execution;
- a multiplexor having a first input coupled to the scheduler to receive dispatched original instructions;
- an execution core, coupled to an output of the multiplexor, for executing instructions, the execution core including
- an ALU, and
- a data cache,
- wherein the execution core performs data speculation upon data which are speculated to be present in the data cache;
- TLB/tag logic coupled to the execution core for performing translation lookaside and tag matching operations on the executed instructions;
- hit/miss logic, coupled to the TLB/tag logic, for detecting whether data operands of the instructions are or are not present in the data cache;
- a checker, coupled to the hit/miss logic, for determining whether the data speculation was erroneous, and coupled to a second input of the multiplexor, for replaying an erroneously data speculated instruction.
Dependencies are inferred from the claim text.