US 5,966,530 A · Structure and method for instruction boundary machine state restoration

Abstract

A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring state at any instruction boundary; (3) tracking instruction status; (4) checkpointing instructions; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state. In one embodiment of the invention, a method of restoring machine state in a processor at any instruction boundary is disclosed. For any instruction which may modify control registers, the processor is either synchronized prior to execution or an instruction checkpoint is stored to preserve state; and for any instruction that creates a program counter discontinuity an instruction checkpoint is stored. Instruction execution status is monitored to detect a fault condition and if a fault occurs, the instruction identifier is saved according to predetermined rules and used as an endpoint to backup the program counter. If the faulting instruction is a checkpointed instruction, then the state information is restored from the checkpoint prior to reexecuting the faulting instruction, but if one of the instructions for which state was stored is sequentially between the faulting instruction and the last issued instruction, then (i) backing-up said processor to the closest checkpoint after the faulting instruction, (ii) back stepping the processor to restore state, and (iii) decrementing the program counter to the faulting instruction.

Claims10

Dependent claims

In a processor having an instruction execution unit, an instruction issue unit, and a memory for storing data within said processor, a method of restoring a prior processor state at any instruction boundary upon detecting a fault or exception condition;

said method comprising:
allocating an instruction serial number for each issued instruction;
storing processor state in a checkpoint within said memory prior to execution only for a first set of executable instructions that will or may alter processor state, said first set of executable instructions being fewer in number than the set of all of the instructions that will or may alter machine state implemented within said processor;
identifying a faulting instruction causing said fault or exception condition, and if multiple such conditions occurred simultaneously, then identifying said faulting instruction as the in order sequentially earliest instruction causing one of said multiple simultaneous conditions;
if said faulting instruction causing said condition is a checkpointed instruction, then restoring a processor state stored prior to execution of said faulting instruction causing said conditions;
if one of said executable instructions for which a processor state information has been stored is sequentially interposed between said faulting instruction causing said condition and the last issued instruction, then:
(i) first, backing-up said processor to the closest checkpoint near said faulting instruction sequentially after said faulting instruction, and
(ii) second, backstepping said processor to restore processor state to the state that existed just prior to execution of said faulting instruction by updating register resources, and
(iii) decrementing a processor program counter associated with said processor to the instruction serial number of said faulting instruction.

6 more elements

A method of restoring machine state in a processor at any instruction boundary comprising:

for any instruction which may modify control registers, either:
(i) synchronizing said machine prior to execution of said instruction, or (ii) storing an instruction checkpoint to preserve machine state prior to execution of said instruction;
and
for any instruction that creates a program counter discontinuity, storing an instruction checkpoint within said processor to preserve architectural and machine state prior to execution of said instruction;
and
monitoring instruction execution to detect an execution exception or fault condition;
saving an instruction identifier of each instruction that results in said execution exception or fault condition;
if more than one executed instruction results in an execution exception or fault condition, determining which of said more than one excepting or faulting instructions occurred sequentially earlier;
using an instruction identifier for said earliest excepting or faulting instruction as an endpoint to backup a program counter in said processor;
if said earliest faulting instruction is a checkpointed instruction, then restoring said machine state stored in the checkpoint prior to execution of said faulting instruction;
and
if one of said instructions for which a machine state has been stored is sequentially interposed between said faulting instruction and the last issued instruction, then (i) backing-up said processor to the closest checkpoint near said faulting instruction after said faulting instruction, (ii) backstepping said processor to restore machine state to the state that existed just prior to execution of said faulting instruction by updating register resources, and (iii) decrementing said processor program counter to the instruction identifier of said faulting instruction.

9 more elements

Dependencies are inferred from the claim text.

Structure and method for instruction boundary machine state restoration

Life of this patent

Structure and method for instruction boundary machine state restoration

Life of this patent

Abstract

Claims10