Processor having auxiliary operand register file and complementary arrangements for non-disruptively performing adjunct execution

A processor capable of executing microcode that references virtual operand registers using virtual addresses having n dimensions, n being a positive integer greater than one, the processor comprising:

• a primary operand register file having a first plurality of operand registers with respective first physical addresses;
• an auxiliary operand register file having a second plurality of operand registers with respective second physical addresses;
• a primary execution unit that executes the microcode and selectively maps the virtual addresses to the first physical addresses of the first plurality of operand registers of the primary operand register file during main execution or to the second physical addresses of the second plurality of operand registers of the auxiliary operand register file at least during interrupt/exception servicing;
• an auxiliary operand register file stack having a capacity for storing a plurality of auxiliary operand register file frames to facilitate nested interrupt/exception servicing, each of the auxiliary operand register file frames consisting of contents of the second plurality of operand registers;
• and
• extended interrupt/exception microcode for pushing an auxiliary operand register file frame onto the auxiliary operand register file stack whenever servicing of a current interrupt/exception is interrupted, and popping a top auxiliary operand register file frame from the auxiliary operand register file stack into the auxiliary operand register file at the end of servicing an interrupt/exception whenever the serviced interrupt/exception preempted an earlier interrupt/exception.

A processor capable of executing microcode that references operand registers using virtual addresses having n dimensions, n being a positive integer greater than one, the processor comprising:

• an instruction fetch unit for fetching microcode instructions from an instruction cache;
• and
• a writable control store facility storing a plurality of implementor-defined micro-trap service routines, each micro-trap service routine comprising a plurality of uninterruptable micro operations;
• wherein the microcode includes micro-trap microcode for dynamically causing the instruction fetch unit to fetch microcode instructions from the writable control store facility rather than the instruction cache responsive to a micro-trap, the micro-trap microcode being further used for forking instruction execution to one of the micro-trap service routines after causing atomicity of operation to be guaranteed to the particular micro-trap service routine.

A processor capable of executing microcode that references operand registers using virtual addresses having n dimensions, n being a positive integer greater than one, the processor comprising:

• an instruction fetch unit for fetching microcode instructions from an instruction cache;
• and
• a writable control store facility storing a plurality of implementor-defined macro library routines, each macro library routine comprising a plurality of interruptable operations;
• wherein the microcode includes macro-trap microcode for dynamically causing the instruction fetch unit to fetch microcode instructions from the writable control store facility rather than from the instruction cache responsive to a macro-trap, the macro-trap microcode being further used for forking instruction execution to one of the macro library routines.

A computer system capable of executing microcode that references operand registers using virtual addresses having n dimensions, n being a positive integer greater than one, the microcode defining a main execution condition and a plurality of adjunct execution conditions, the computer system comprising:

• a primary operand register file having a first plurality of N operand registers with respective first physical addresses, wherein the total number of virtual addresses in each of the n dimensions is a geometric factor of N.sup.1/(n+1) ;
• an auxiliary operand register file having a second plurality of N operand registers with respective second physical addresses, wherein the total number of virtual addresses in each of the n dimensions is a geometric factor of N.sup.1/(n+1) ;
• and
• a primary execution unit that executes the microcode and maps the virtual addresses to the first and second physical addresses in response to the microcode, the primary executing unit including:
• selecting means for causing all of the virtual addresses to be mapped to the first physical addresses of the first plurality of operand registers of the primary operand register file during the main execution condition and for causing all of the virtual addresses to be mapped to the second physical addresses of the second plurality of operand registers of the auxiliary operand register file during all of the adjunct execution conditions.

A computer system capable of executing microcode that references operand registers using virtual addresses having n dimensions, n being a positive integer greater than one, the computer system comprising:

• a primary operand register file having a first plurality of operand registers with respective first physical addresses;
• an auxiliary operand register file having a second plurality of operand registers with respective second physical addresses;
• a primary execution unit that executes the microcode and selectively maps the virtual addresses to the first physical addresses of the first plurality of operand registers of the primary operand register file during main execution or to the second physical addresses of the second plurality of operand registers of the auxiliary operand register file at least during interrupt/exception servicing;
• and
• an auxiliary operand register file stack having a capacity for storing a plurality of auxiliary operand register file frames, to facilitate nested interrupt/exception servicing, each of the auxiliary operand register file frames consisting of contents of the second plurality of operand registers.

A computer system capable of executing microcode that references operand registers using virtual addresses having n dimensions, n being a positive integer greater than one, the computer system comprising:

• an instruction fetch unit for fetching and dispatching microcode instructions from an instruction cache;
• and
• a writable control store facility storing a plurality of implementor-defined micro-trap service routines, each micro-trap service routine comprising a plurality of uninterruptable micro operations,
• wherein the microcode includes micro-trap microcode for dynamically causing the instruction fetch unit to fetch microcode instructions from the writable control store facility rather than from the instruction cache responsive to a micro-trap, the micro-trap microcode being further used for forking instruction execution to one of the micro-trap service routines.

A computer system capable of executing microcode that references operand registers using virtual addresses having n dimensions, n being a positive integer greater than one, the computer system comprising:

• an instruction fetch unit for fetching and dispatching microcode instructions from an instruction cache;
• and
• a writable control store facility storing a plurality of implementor-defined macro-trap library routines, each macro-trap library routines comprising a plurality of interruptable operations,
• wherein the microcode includes macro-trap microcode for dynamically causing the instruction fetch unit to fetch microcode instructions from the writable control store facility rather than from the instruction cache responsive to a macro-trap, the macro-trap being further used for forking instruction to one of the macro library routines.