Multi-phase clock distribution method and system for complex integrated-circuit devices

A method for efficiently distributing a plurality of diverse clock phase signals throughout a complex integrated circuit device which includes multiple parallel rows of logic circuits, said method comprising the steps of:

• laying out n substantially parallel clock lines traversing said complex integrated circuit device, each of said n substantially parallel clock lines distributing a single diverse clock phase signal to logic circuits in an associated parallel row of logic circuits;
• disposing at least one substantially vertical region within said complex integrated circuit device, said at least one substantially vertical region traversing each of said n substantially parallel clock lines;
• and
• disposing a plurality of clock regenerator cells within said at least one substantially vertical region, each of said plurality of clock regenerator cells coupled to one of said n substantially parallel clock lines such that an individual diverse clock phase signal may be coupled to any of said multiple parallel rows of logic circuits through a span of not greater than n-1 parallel rows of logic circuits such that clock skew is minimized.