System and method for analyzing static timing

A static-timing analysis method for ICs which outputs potential critical paths based on transistor-connection information, comprising:

• a net-list input step which inputs a net list of per-transistor basis connection information, to construct an internal data structure for analysis;
• an expected-value check step which checks one or more nodes of said integrated circuits and extracts those of said nodes whose expected values cannot be a high-impedance state from among those of said nodes contained in said internal data structure;
• a signal-flow direction narrow-down step which narrows down directions in which transistor signals flow, based on information obtained by said expected-value check step;
• a path search step which searches potential critical paths with reference to directions narrowed down in which a signal may flow;
• and
• an output step which outputs paths which have been searched by said path search step.

A computer program product comprising a computer useable medium having computer program logic recorded thereon for enabling a processor in a computer system to perform static-timing analysis of an integrated circuit (IC), said computer program logic comprising:

• means for enabling the processor to input a net list of per-transistor basis connection information to construct an internal data structure for analysis;
• means for enabling the processor to check nodes of the integrated circuit and extract those of said nodes whose expected values cannot be a high-impedance state from among those of said nodes contained in said internal data structure;
• means for enabling the processor to narrow down directions in which transistor signals flow from said expected values;
• means for enabling the processor to search potential critical paths with reference to the directions narrowed down in which the signal may flow;
• and
• means for enabling the processor to output paths which have been searched.