Parallel emulation system and method

An emulator for use in emulating computer functions specified by a plurality of program instructions, the emulator comprising:

• a memory arrangement including a plurality of memory locations, wherein each of the memory locations includes a status indicator;
• and
• a pipelined processing arrangement including at least one processing unit to process a plurality of activity routines, the processing arrangement coupled to the memory arrangement to form stages of alternating activity routines and memory locations for concurrently providing isolated emulation functions at each stage, wherein the processing arrangement is configured and arranged to:
• emulate one of the computer functions designated by the program instructions at each activity routine;
• modify a state of the status indicators upon availability of the respective memory locations, wherein the modification of the status indicators is independent of any particular clock cycle;
• asynchronously transfer the program instructions from the activity routines to their associated memory locations, when the corresponding status indicators indicate that the respective memory locations are available;
• and
• asynchronously transfer the program instructions from the memory locations to the activity routines of successive stages, when the corresponding status indicators indicate that the respective memory locations are holding available program instructions.

A pipelined emulation system for emulating computer hardware under the control of a plurality of program instructions, wherein the program instructions are received by the emulation system, the emulation system comprising:

• a memory bank having a plurality of memory locations, wherein each of the memory locations includes at least one status bit;
• a plurality of processing units coupled to successively receive the program instructions, each having an input to receive information from a preceding one of the memory locations, and each further having an output to provide information to a succeeding one of the memory locations;
• and
• a plurality of computer-readable mediums corresponding to each of the plurality of processing units, each having computer program code embodied thereon, the computer program code including:
• first program code means for emulating one of a plurality of functions designated by each of the program instructions at each of the processing units;
• asserting the status bit at a particular memory location when execution of its corresponding function has completed:
• second program code means for forwarding information from each of the processing units to succeeding ones of the processing units when a given processing unit has completed its function and has recognized that the status bit for its succeeding processing unit has been asserted.

A method of providing parallel emulation of a plurality of program instructions, comprising the steps of:

• sequentially providing a plurality of program instructions to a series of activity routines;
• emulating one of a plurality of functions designated by each of the program instructions at each stage of the series of activity routines;
• forwarding information from each of the stages of the series of activity routines to their successive stages in the series, wherein each stage forwards its associated information to its respective successive stage when the stage has completed its function and has recognized that its respective successive stage has completed its respective function;
• and
• wherein forwarding information further comprises asynchronously passing the information through the stages of the series of activity routines.

An emulator for use in emulating computer functions specified by a plurality of program instructions, the emulator comprising:

• a memory arrangement including a plurality of memory locations, wherein each of the memory locations includes a status indicator;
• a processing arrangement including a first processing unit to process a plurality of activity routines, the processing arrangement coupled to the memory arrangement to form stages of alternating activity routines and memory locations for concurrently providing isolated emulation functions at each stage, wherein the processing arrangement is configured and arranged to:
• emulate one of the computer functions designated by the program instructions at each activity routine;
• transfer the program instructions from the activity routines to their associated memory locations, when the corresponding status indicators indicate that the respective memory locations are available;
• and
• transfer the program instructions from the memory locations to the activity routines of successive stages, when the corresponding status indicators indicate that the respective memory locations are holding available program instructions;
• and
• wherein the processing arrangement further comprises a duplicative processing unit configured and arranged to duplicate one of the activity routines in a corresponding stage, and wherein resulting duplicate activity routines concurrently process alternate ones of the program instructions.