Microprocessor for supporting reduction of program codes in size

A microprocessor for supporting reduction of codes in size, comprising:

• a buffer array for including, for reuse, n operand address buffers which respectively store from an immediately preceding target memory access address to a target memory access n times previously used in past accesses to said external memory, wherein n is an integer of 2 or larger, and wherein buffer array is connected to an external memory;
• a fetching means for fetching an instruction;
• an instruction detecting means for detecting an instruction which has been fetched by said fetching means and is to access said external memory;
• a judging means for judging whether said instruction detected by said instruction detecting means specifies any of said operand address buffers;
• a first controlling means for controlling said buffer array so that said address buffer is output to said external memory if said judging means judges that said instruction detected by said instruction detecting means specifies said operand address buffer, and
• a second controlling means for storing an address obtained from an operand of said instruction detected by instruction detecting means into any of said operand address buffers and controlling said buffer array so that said stored address is output to said external memory if said judging means judges that said instruction does not specify any operand address buffers.

A microprocessor for supporting reduction of program codes in size, comprising:

• a decoder for decoding instructions which are "W" in length represented by expression
• w=a+nb,
• wherein "a" represents a length of code at each decoding by said decoder, "n" represents an integer of 0 or larger, and "b" represents a positive integer smaller than "a," wherein "b" represents a bit length called a half word when "a" represents a bit length called a word, wherein a half word is a half of a word in length, an instruction is divided into one or more codes, and wherein said instructions include at least an instruction which is "a" in length and an instruction which is "(a+b)" in length;
• an executing means for processing data based on information obtained from said instructions decoded by said decoder;
• an instruction buffer for holding a prefetched instruction;
• a storage means for storing a state of said instruction held in said instruction buffer for each half word;
• a first judging means for judging whether a code to be decoded next is a half word or a word in length based on information obtained from an instruction decoded by said decoder;
• and
• a controlling means for controlling said instruction buffer based on said length judged by said first judging means and said state stored in said storage means so that a code of said instruction stored in said instruction buffer is transferred to said decoder and for updating said state stored in said instruction buffer;
• wherein said decoder comprises:
• an upper-order decoding register for storing an upper-order half word of a code;
• and
• a lower-order decoding register for storing a lower-order half word of said code;
• wherein said instruction buffer comprises:
• a first register for storing a word code fetched latest;
• said first register comprising a first upper-order register for storing an upper-order half word of a code and a first lower-order register for storing a lower-order half word of said code;
• a second register for storing a word code which precedes said code stored in said first register;
• said second register comprising a second upper-order register for storing an upper-order half word of a code and a second lower-order register for storing a lower-order half word of said code;
• and
• a selecting means for selectively transfering a code to said decoder based on a direction from said controlling means;
• wherein said selecting means comprises:
• an upper-order selecting means for selectively transferring a code to said upper-order decoding register from any of said second upper-order register, said second lower-order register, and said lower-order decoding register;
• and
• a lower-order selecting means for selectively transferring a code to said lower-order decoding register from any of said second upper-order register, said second lower-order register, and said first lower-order register;
• wherein said storage means stores any of a first state which indicates that any of said second upper-order register and said second lower-order register does not store a code, a second state which indicates that said second upper-order register stores a code and said second lower-order register does not store a code, and a third state which indicates that each of said second upper-order register and said second lower-order register store a code.