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US 5,966,474 AGranted
Non-symmetric radial and non-symmetric pruned radial interpolation
AssigneeHewlett-Packard Company
InventorGary L. Vondran, Jr.
Life of this patent
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AssigneeHewlett-Packard Company
InventorGary L. Vondran, Jr.
Estimating the term…
New interpolation techniques allow improved efficiency and speed in performing color space conversions. A radial interpolation technique accomplishes an interpolation by generating successive subcubes. A value of a vertex of the final subcube generated is used as the result of the interpolation. Subcubes are generated by averaging a selected vertex value with the vertex values of each of the remaining vertices. A pruned radial interpolation technique employs a subset of the vertex values of the initially selected cube to generate the result of the interpolation, thereby improving upon the efficiency of the radial interpolation. A tetrahedral interpolation technique accomplishes an interpolation by generating successive subcubes. A value of a vertex of the final subcube generated is used as the result of the interpolation. Subcubes are generated by applying a mathmatical relationship which allows computation of subcube vertex values through a series of logical AND, logical OR and averaging operations. A pruned tetrahedral interpolation technique employs a subset of the vertex values of the initially selected cube to generate the result of the interpolation, thereby improving upon the efficiency of the tetrahedral interpolation. A common hardware implementation of pruned radial interpolation and pruned tetrahedral interpolation uses the common hardware structure of the two techniques with multiplexing of the input vertex values to allow performance of either a pruned radial interpolation or a pruned tetrahedral interpolation. Non-symmetric pruned radial and Non-symmetric pruned tetrahedral interpolation permit interpolation using interpolation data values distributed throughout the color space with a resolution that varies according to characteristics of the color space. Multiplexing of the interpolation data values to the non-symmetric pruned radial interpolation hardware and to the non-symmetric pruned tetrahedral interpolation hardware allows for a common hardware implementation.
A non-symmetric pruned radial interpolator for interpolating between interpolation data values using input data values each having d components to generate output data values, said d components represented, correspondingly, by d sets of bits each partitioned to form d sets of lower order bits each having, respectively, n.sub.1, n.sub.2, n.sub.3, . . . n.sub.d of said bits, said non-symmetric pruned radial interpolator comprising:
A non-symmetric radial interpolator for interpolating between interpolation data values using input data values each having d components to generate output data values, said d components represented, correspondingly, by d sets of bits each partitioned to form d sets of lower order bits each having, respectively, n.sub.1, n.sub.2, n.sub.3, . . . n.sub.d of said bits, said non-symmetric radial interpolator comprising:
A method of non-symmetric pruned radial interpolation with interpolation data values for selection using input data values each having d components, said d components represented by d sets of bits each partitioned to form d sets of higher order bits and d sets of lower order bits with said d sets of lower order bits each having, respectively, n.sub.1, n.sub.2, n.sub.3, . . . n.sub.d of said bits, said d sets of lower order bits designated as 1b.sub.1, 1b.sub.2, . . . , 1b.sub.d with a bit position of each bit of said d sets of lower order bits designated from a most significant of said lower order bits to a least significant of said lower order bits by corresponding values of i.sub.1, i.sub.2, i.sub.3 . . . , i.sub.d each ranging, correspondingly, from n.sub.1 -1 to 0, n.sub.2 -1 to 0, n.sub.3 -1 to 0, . . . n.sub.d -1 to 0, comprising the steps of:
A method of non-symmetric radial interpolation with interpolation data values for selection using input data values each having d components, said d components represented by d sets of bits each partitioned to form d sets of higher order bits and d sets of lower order bits with said d sets of lower order bits each having, respectively, n.sub.1, n.sub.2, n3, . . . n.sub.d of said bits, said d sets of lower order bits designated as 1b.sub.1, 1b.sub.2, . . , 1b.sub.d with a bit position of each bit of said d sets of lower order bits designated from a most significant of said lower order bits to a least significant of said lower order bits by corresponding values of i.sub.1, i.sub.2, i.sub.3, . . . i.sub.d each ranging, correspondingly, from n.sub.1 -1 to 0, n.sub.3 -1 to 0, n.sub.2 -1 to 0, . . . n.sub.d -1 to 0, comprising the steps of:
Dependencies are inferred from the claim text.