Emulation of an m bit counter driven by a desired clock frequency given a central clock frequency

An m bit counter that counts to a desired clock frequency F.sub.D from a central clock frequency F.sub.C, a ratio of the central clock frequency over the desired clock frequency r=F.sub.C /F.sub.D =2.sup.n *p, wherein n is one of zero and an integer and wherein p is an odd number integer, the m bit counter comprising:

• a first subcounter which counts from one to p driven by the central clock frequency to generate a pulse of an intermediate clock frequency for every periodic count from one to p;
• a second subcounter which counts m+n bits, including m bits of the m bit counter with an appended n bits as least significant bits, driven by the intermediate clock frequency generated by the first subcounter;
• whereby m most significant bits of the second subcounter counts as the m bit counter to the desired clock frequency F.sub.D ;
• wherein the second subcounter increments by a bit in counting m+n bits when the m bit counter is an incrementing counter, and wherein the second subcounter decrements by a bit in counting m+n bits when the m bit counter is a decrementing counter;
• wherein at least one of the desired clock frequency F.sub.D and the central clock frequency F.sub.C is variable, and wherein the m bit counter further comprises:
• a data processor which determines n and p for r=F.sub.C /F.sub.D =2.sup.n *p, wherein n is one of zero and an integer and wherein p is an integer, for each variation in at least one of the desired clock frequency F.sub.D and the central clock frequency;
• and
• a counter controller for controlling the first subcounter to count from one to p to generate a pulse of an intermediate clock frequency for every periodic count from one to p, and for controlling the second subcounter to append n bits as least significant bits in the m+n bit count, for each variation in at least one of the desired clock frequency F.sub.D and the central clock frequency F.sub.C.