Cycle alignment circuit for multicycle time systems

Abstract

A chip-to-chip Cycle Alignment Circuit is implemented on the CP chip with a phased lock loop so that a chip knows what is the cycle of a connected chip. Once the PLL is locked, the timing relationship is developed between a reference oscillator and the 3.5 ns on-chip clock which clocks three latches (latch 1,2,3). The Cycle Alignment Circuit has a first part for a rising edge detecting clock chopper and the second part for a self resetting toggle latch. The rising edge detecting clock chopper works by detecting the reference oscillator's rising edge after it has gone through a small delay. The purpose of this delay is to ensure that a latch 1 detects the rising edge on the second 3.5 ns cycle after the reference oscillator rises. A latch 2 is then used to generate a one (3.5 ns) cycle pulse at point that starts on the second 3.5 ns cycle and ends on the third 3.5 ns cycle. The pulse that is produced at that point forces a latch 3 to be reset to a 1 at the beginning of cycle 3. Once the pulse at that point goes away, latch 3 simply toggles every 3.5 ns cycle. This operation will be repeated as spaced times when the reference oscillator rises. Every successive spaced time the pulse at that point is generated, the other leg of the OR gate feeding latch 3 will also be high so the toggle function of latch 3 will be preserved. This circuit can easily be used to align chips with cycle time differences of two, as well as those other than a factor of two.

Dependencies are inferred from the claim text.