Bus driving system and integrated circuit device using the same

A bus system, comprising:

• a bus driving system including:
• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;
• a driver circuit for driving said bus wires at said transmitting end;
• a charge circuit for charging wiring capacitance of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;
• control wires for redistributing wiring capacitance of said bus wires;
• a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires;
• and
• a detection circuit for detecting data signals from said bus wires at said receiving end;
• and
• a bus interface for interconnecting execution/control means, memory means storing data signals and an external bus to one another via said bus driving system.

In an information processing system which comprises antenna means for transmitting and receiving a radio signal, a modulator/demodulator circuit for converting said signal supplied from said antenna means, at least one of a digital-to-analogue converter for converting said signal into an analogue signal and an analogue-to-digital converter for converting said signal into a digital signal, and memory means for storing information;

• a base band LSI (Large Scale Integrated circuit) for controlling said information processing system, comprising:
• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;
• a driver circuit for driving said bus wires at said transmitting end;
• a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;
• control wires for redistributing wiring capacitances of said bus wires;
• a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires;
• and
• a detection circuit for detecting data signals from said bus wires at said receiving end;
• arithmetic means for arithmetically determining data to be sent to said information processing system;
• data address control means for controlling addresses of said data;
• instruction-dedicated read-only memory means for storing instructions commanding operations of said information processing system;
• program control means for controlling operations of said information processing system;
• and
• bus interface means for connection to said information processing system.

An integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips,

• said bus system including a bus driving system which comprises:
• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;
• a driver circuit for driving said bus wires at said transmitting end;
• a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;
• control wires for redistributing wiring capacitances of said bus wires;
• a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires;
• and
• a detection circuit for detecting data signals from said bus wires at said receiving end.

An integrated circuit device including a plurality of chips mounted on a package board and a bus system for interconnecting said chips,

• said bus system including a bus driving system which comprises:
• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;
• a driver circuit for driving said bus wires at said transmitting end;
• a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end;
• control wires for redistributing wiring capacitances of said bus wires;
• a switch circuit for discharging electric charge stored in said wiring capacitances of said control wires;
• and
• a detection circuit for detecting data signals from said bus wires at said receiving end,
• said integrated circuit device being implemented in the form of a package;
• wherein at least a power source wire, a ground wire and said control wires are led out to corresponding pins of said package.

A bus driving system for transmitting data of n bits (where n is a positive integer), comprising:

• (n+2) wires including first to (n+2)-th wires;
• at least one set of (n+1) switching circuits including first to (n+1)-th switching circuits;
• means for making potentials at said first to (n+1)-th wires coincide with a level of a first operation potential level;
• and
• means for making potential at said (n+2)-th wire coincide with a second operation potential level;
• wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+1)) controls conduction and non-conduction between said k-th wire and said (n+2)-th wire;
• said first to n-th switching circuits responding to said first to n-th bit signals, respectively;
• and
• wherein said first to (n+1)-th switching circuits respond to a first control signal.

A microprocessor including a bus driving system for driving a n-bit data bus (where n is a positive integer),

• said bus driving system comprising:
• (n+2) wires including first to (n+2)-th wires;
• at least one set of (n+1) switching circuits including first to (n+1)-th switching circuits;
• means for making potentials at said first to (n+1)-th wires coincide with a level of a first operation potential level;
• and
• means for making potential at said (n+2)-th wire coincide with a second operation potential level;
• wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+1)) controls conduction and non-conduction between said k-th wire and said (n+2)-th wire;
• said first to n-th switching circuits responding to said first to n-th bit signals, respectively;
• and
• wherein said first to (n+1)-th switching circuits respond to a first control signal.

A package board including a plurality of chips mounted on a board, and a bus driving system used as an external bus for interconnection of said chips,

• said bus driving system comprising:
• (n+2) wires including first to (n+2)-th wires;
• at least one set of (n+1) switching circuits including first to (n+1)-th switching circuits;
• means for making potentials at said first to (n+1)-th wires coincide with a level of a first operation potential level;
• and
• means for making potential at said (n+2)-th wire coincide with a second operation potential level;
• wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+1)) controls conduction and non-conduction between said k-th wire and said (n+2)-th wire;
• said first to n-th switching circuits responding to said first to n-th bit signals, respectively;
• and
• wherein said first to (n+1)-th switching circuits respond to a first control signal.

A large scale integrated circuit (LSI) comprising:

• an integrated circuit;
• and
• a plurality of input/output ports, connected to said integrated circuit, operating in synchronism with a clock signal,
• wherein one of high and low levels at each of said input/output ports remains constant independent of operation cycles, while the other of said high and low levels is changed depending on the operation cycles.

A bus driving system for driving a bus for data of n bits (where n is a positive integer), comprising:

• (n+1) wires including first to (n+1)-th wires;
• at least one set of n switching circuits including first to n-th switching circuits;
• means for making potentials at said first to n-th wires coincide with a first operation potential level;
• and
• means for making potential at said (n+1)-th wire coincide with a second operation potential level;
• wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than n) controls conduction and non-conduction between said k-th wire and said (n+1)-th wire,
• said first to n-th switching circuits responding to said first to n-th bit signals and a first control signal, respectively.

A bus driving system, comprising:

• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;
• a driver circuit provided at said transmitting end for driving said bus wires;
• a control circuit for redistributing wiring capacitances of transmission lines formed by said bus wires;
• and
• a detection circuit provided at said receiving end for detecting bus signals,
• said control signals being delivered from first to fourth control wires;
• wherein said first control wire is usually at zero level and assumes an intermediate level between a level substantially equal to the supply voltage level and a level substantially equal to the ground level upon redistribution of the wiring capacitances of the transmission lines formed by said bus wires;
• said second and third control wires are usually at said supply voltage level and assume an intermediate level between a level substantially equal to the supply voltage level and a level substantially equal to the ground level upon redistribution of the wiring capacitances of the transmission lines formed by said bus wires, respectively;
• and
• wherein said fourth wire is disposed adjacent to said second and third control lines and usually at said supply voltage level while assuming a level substantially equal to said supply voltage level upon redistribution of the wiring capacitances of the transmission lines formed by said bus wires.

A bus driving system for transmitting data of n bits (where n is a positive integer), comprising:

• (n+4) wires including first to (n+4)-th wires;
• at least one set of (n+2) switching circuits including first to (n+2)-th switching circuits;
• means for making potentials at said first to (n+3)-th wires coincide with a level of a first operation potential level;
• and
• means for making potential at said (n+4)-th wire coincide with a second operation potential level;
• wherein a k-th switching circuit (where k is a given integer greater than 1 (one) and smaller than (n+2)) controls conduction and non-conduction between said k-th wire and said (n+4)-th wire;
• said first to n-th switching circuits responding to said first to n-th bit signals, respectively;
• and
• wherein said first to (n+2)-th switching circuits respond to a first control signal.

A driver circuit including a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire, and an n-channel MOS transistor having a source-drain path connected between said output wire and a circuit point of a second operation potential level, wherein gates of said p-channel MOS transistor and said n-channel MOS transistor responds to a data input signal, whereby an output signal relevant to said data input signal is delivered onto said output wire,

• said driver circuit further comprising:
• a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level;
• and
• a control circuit controlled by a precharge signal, an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;
• wherein the gate of said n-channel MOS switching transistor is controlled by said precharge control signal.

A semiconductor integrated circuit which comprises a chip incorporating therein a CPU, a memory, a peripheral circuit and an internal bus, and a driver circuit disposed between said internal bus and at least one of said CPU and said peripheral circuit,

• said driver circuit including:
• a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire;
• an n-channel MOS transistor having a source-drain path connected between said output wire, and a circuit point of a second operation potential level;
• gates of said p-channel MOS transistor and said n-channel MOS transistor responding to a data input signal, to thereby deliver an output signal relevant to said data input signal onto said output wire;
• a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level;
• and
• a control circuit controlled by a precharge signal, an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;
• wherein the gate of said n-channel MOS switching transistor is controlled by said precharge control signal.

A driver circuit including a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire, and an n-channel MOS transistor having a source-drain path connected between said output wire and a circuit point of a second operation potential level, wherein gates of said p-channel MOS transistor and said n-channel MOS transistor responds to a data input signal, whereby an output signal relevant to said data input signal is delivered onto said output wire,

• said driver circuit further comprising:
• a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level;
• and
• a control circuit controlled by an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;
• wherein the gate of said n-channel MOS switching transistor is driven by a signal of a phase opposite to that of the signal driving the gate of said n-channel MOS transistor.

A semiconductor integrated circuit which comprises a chip incorporating therein a CPU, a memory, a peripheral circuit and an internal bus, and a driver circuit disposed between said internal bus and at least one of said CPU and said peripheral circuit,

• said driver circuit including:
• a p-channel MOS transistor having a source-drain path connected between a circuit point of a first operation potential level and an output wire;
• an n-channel MOS transistor having a source-drain path connected between said output wire, and a circuit point of a second operation potential level;
• gates of said p-channel MOS transistor and said n-channel MOS transistor responding to a data input signal, to thereby deliver an output signal relevant to said data input signal onto said output wire;
• a parallel connection of a source-drain path of an n-channel MOS switching transistor and a capacitor, said parallel connection being inserted between a source terminal of said n-channel MOS transistor and said circuit point of said second operation potential level;
• and
• a control circuit controlled by an enable signal controlling drive and floating states of said driver circuit and said data input signal, to thereby control the gate of said p-channel MOS transistor and the gate of said n-channel MOS transistor;
• wherein the gate of said n-channel MOS switching transistor is driven by a signal of a phase opposite to that of the signal driving the gate of said n-channel MOS transistor.

An information processing system comprising:

• antenna means for transmitting and receiving a radio signal;
• a modulator/demodulator circuit for converting said signal supplied from said antenna means;
• a digital-to-analog converter for converting said signal into an analog signal;
• an analog-to-digital converter for converting said signal into a digital signal;
• a memory means for storing information;
• and
• an integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system comprising:
• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals,
• a driver circuit provided at said transmitting end for driving said bus wires,
• a control circuit for redistributing wiring capacitances of transmission lines formed by said bus wires, and
• a detection circuit provided at said receiving end for detecting bus signals.

An integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system comprising:

• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals;
• a driver circuit provided at said transmitting end for driving said bus wires;
• a control circuit for redistributing wiring capacitances of transmission lines formed by said bus wires;
• and
• a detection circuit provided at said receiving end for detecting bus signals.

An information processing system comprising:

• antenna means for transmitting and receiving a radio signal;
• a modulator/demodulator circuit for converting said signal supplied from said antenna means;
• a digital-to-analog converter for converting said signal into an analog signal;
• an analog-to-digital converter for converting said signal into a digital signal;
• a memory means for storing information;
• and
• an integrated circuit including a plurality of chips mounted on a package board and a bus system for interconnecting said chips, said bus system including a bus driving system comprising:
• bus wires wired between a transmitting end and a receiving end for carrying a plurality of data signals and control signals,
• a driver circuit for driving said bus wires at said transmitted end,
• a charge circuit for charging wiring capacitances of transmission lines formed by said bus wires and extending from said transmitting end to said receiving end,
• control wires for redistributing wiring capacitances of said bus wires,
• a switch circuit for discharging an electric charge stored in said wiring capacitances of said control wires, and
• a detection circuit for detecting data signals from said bus wires at said receiving end.