High-speed test system for a memory device

A circuit device comprising:

• a plurality of circuit cells operable to store data therein, the plurality of circuit cells including first and second sub-arrays of circuit cells;
• a plurality of output terminals, including first and second output terminals coupled to the first and second sub-arrays, respectively;
• a control circuit coupled to the first and second sub-arrays and being operable to transfer data from the first and second sub-arrays to the first and second output terminals, respectively;
• a test circuit coupled to the control circuit and the first and second sub-arrays, the test circuit, in response to a predetermined signal, testing data written to the first sub-array and outputting a test signal based on the testing;
• and
• a switch coupled to the test circuit and one of the plurality of output terminals, the switch receiving the predetermined signal from the control circuit and coupling the test circuit to the one output terminal in response thereto.

A semiconductor memory device comprising:

• a plurality of memory cells operable to store data therein, the plurality of memory cells including first and second sets of sub-arrays of memory cells, each set having eight sub-arrays corresponding to a data word;
• a control circuit coupled to the plurality of memory cells and being operable to write data to, and read data from, the plurality of memory cells;
• and
• a test circuit having first and second compare circuits, the first compare circuit comparing bits in a first data word written to the first set of sub-arrays to each other and outputting a pass value for a test signal if all of the bits in the first data word match, and the second compare circuit comparing bits in a second data word written to the second set of sub-arrays to each other and to at least one bit from the first data word and outputting a pass value for the test signal if all of the bits of the second data word and the one bit from the first data word match.

A computer system comprising:

• an input device;
• an output device;
• an address bus;
• a data bus;
• a set of control lines;
• a memory controller coupled to the address and data buses and to the set of control lines;
• a processor coupled to the input and output devices, to the address and data buses and to the set of control lines;
• and
• a memory device coupled to the memory controller through the address and data buses and the set of control lines, the memory device comprising:
• an array of memory cells operable to store data therein;
• a plurality of output terminals;
• a control circuit coupled to the array of memory cells and being operable to transfer data from at least one memory cell to one of the output terminals during a read operation;
• a test circuit coupled to the control circuit and array of memory cells, the test circuit, in response to a test mode signal, testing data written to at least one memory cell of the array during the read operation and outputting a test signal based on the testing to one of the output terminals;
• and
• a data path coupling at least one of the memory cells being tested by the test circuit to one of the output terminals during the read operation.

A semiconductor device testing apparatus comprising:

• a die having a semiconductor circuit formed thereon, the semiconductor circuit having a plurality of memory cells operable to store data therein;
• a plurality of electrically conductive leads coupled to the semiconductor circuit on the die, the leads including address leads for receiving address signals, and wherein the plurality of memory cells are addressable by electrically conductive row and column lines based on an address word applied to the address leads;
• a control circuit coupled to the memory cells and being operable to transfer data from the memory cells to one of the first and second leads;
• a test circuit coupled to the control circuit and the memory cells, the test circuit testing data written to at least one memory cell and outputting a test signal based on the testing to one of the leads;
• a data path coupling at least one of the memory cells being tested by the test circuit to one of the leads during the read operation;
• an encapsulating material that encapsulates the die and at least a portion of the plurality of leads to form a packaged chip;
• testing circuitry for applying the address signals;
• and
• a socket for releasably holding the packaged chip and electrically coupling the plurality of leads with the testing circuitry.

A method of testing a semiconductor memory device having an array of memory cells and at least one output terminal, the method comprising the steps of:

• entering into a test mode;
• writing data to at least one memory cell of the array;
• testing the data written to the memory cell;
• providing a test signal indicating the results of the testing;
• selectively providing the test signal to one of the output terminals when the memory device is in the test mode;
• and
• reading the data from the memory cell and providing the data to one of the output terminals.

A method of testing a semiconductor memory device having first and second sets of memory cells, the method comprising the steps of:

• writing first and second sets of data to the first and second sets of memory cells;
• reading the first set of data from the first set of memory cells and comparing the first set of data with itself;
• reading the second set of data from the second set of memory cells and comparing the second set of data to itself and to at least one bit from the first set of data;
• and
• generating a test signal based on the reading steps.