A data communication system employing time division multiplexing in which each data frame is divided into P number of time slots, the system comprising:
- a processor;
- a bus means for transferring data connected to said processor;
- identical first and second interface modules, each of said interface modules connected to said processor via said bus means, said first and second interface modules having a communication link therebetween configured to signal which of the two interface modules is in an active state and which of the two interface modules is in a stand-by state at any given time;
- a first set of N number of devices, each device of said first set having a data communication path to said first interface module, a second set of N number of devices, each device of said second set having a data communication path to said second interface module, with N being not greater than P and each device in both sets of N devices further configured to provide a status signal to both of said first and second interface modules, N being not greater than P;
- wherein
- each of a first number of devices in said first set specifies a default number of time slots, upon initiation of data communication;
- said processor is configured to determine, for each of the first number of devices, an adaptive number of time slots based on said default number of time slots and an available number of time slots;
- each of the first number of devices modifies said default number of time slots, in response to said adaptive number of time slots;
- and
- said first interface module assigns time slots to each of the first number of devices, based on said adaptive number for that device, wherein the first interface module includes:
- a processor interface block for processing signals including a clock signal and a mode selection signal and a frame;
- a consolidation block for receiving the frame and a modified time selection signal from said each device;
- a loop-back block for receiving the mode selection signal from the processor interface block and the frame from the processor and the consolidation block, wherein the frame received from the processor and the consolidation block is looped back to the processor if the mode selection signal indicates a loop-back mode, and if otherwise, the frame is sent to the processor interface block;
- a distribution block for receiving the clock signal and the frame from the processor interface block and generating the time slot selection signal;
- and
- an alarm gathering block for generating alarm signals for each device, each alarm signal indicating whether there is an open cable.