Variable latency memory circuit
AssigneeTexas Instruments Incorporated
InventorPaulette Thurston
Life of this patent
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Abstract
A memory integrated circuit includes a memory cell array, data lines 211 for transferring data to and from the memory cell array, data storage circuitry 200 coupled between the memory cell array and the data lines, and programmable circuitry 202, 206, 208 coupled to the data storage circuitry and responsive to control inputs and a clock signal for releasing data in the data storage circuitry. In further embodiments, the data storage circuitry includes a latch and the programmable circuitry includes circuitry for counting a predetermined number of cycles of the clock signal prior to releasing data in the data storage circuitry. The integrated circuit may also include circuitry 302 for transferring data to or from said array in a burst comprising a plurality of data bits.
Claims21
A memory integrated circuit, comprising:
- a memory cell array;
- data lines for transferring data to and from said memory cell array;
- data storage circuitry coupled between said memory cell array and said data lines;
- a mode register circuit coupled to receive latency data, the mode register circuit arranged to produce a latency signal;
- and
- a counter circuit coupled to receive the latency signal from the mode register circuit, the counter circuit coupled to the data storage circuitry, the counter circuit arranged to inhibit said transferring data in said data storage circuitry prior to a predetermined state of said latency signal and a clock signal, the counter circuit arranged to release said data in said data storage circuitry in response to said predetermined state.
A memory integrated circuit, comprising:
- a memory cell array;
- a clock signal input;
- data lines for transferring data to and from said memory cell array;
- latches coupled between said memory cell array and said data lines for storing data to be transferred to or from said memory cell array;
- a mode register containing latency input data;
- and
- a counting circuit coupled to said mode register, said latches, and said clock signal input, said counting circuit providing a signal to release data from said latches after the lapse of a predetermined number of cycles of said clock signal, said predetermined number of cycles corresponding to said latency input data.
A method for coordinating input and output of data from a memory cell array with a clock signal, said method comprising the steps of:
- storing data to be transferred to or from said memory cell array in data storage circuitry connected to said memory cell array;
- counting a predetermined number of cycles of said clock signal;
- providing a signal to said data storage circuitry after the lapse of said predetermined number of clock cycles;
- and
- releasing said stored data.
Dependencies are inferred from the claim text.