Write control driver circuit and method
AssigneeLG Semicon Co., Ltd.
InventorJoon-Ho Na
Life of this patent
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Abstract
A write control driver circuit stores a data in a high speed chip by causing an enabling timing of a write control signal to become faster. The circuit includes a first logic circuit for receiving a peri-top address transition detection signal and a peri-bottom address transition detection signal, and a second logic circuit for receiving a combined address transition detection signal, a coding signal and a write driver signal, each having a predetermined width. The combined address transition detection signal is generated based on a delay unit having a prescribed pulse width. The second logic circuit outputs a write control signal that is not controlled by the peri-top address transition detection signal and the peri-bottom address transition detection signal.
Claims20
A write control driver circuit, comprising:
- a first logic circuit that receives a peri-top address transition detection signal and a peri-bottom address transition detection signal;
- and
- a second logic circuit that receives a combined address transition detection signal, a coding signal and a write driver signal each having a predetermined width, wherein the second logic current outputs a write control signal that is not controlled by the peri-top address transition detection signal and the peri-bottom address transition detection signal.
A write control driver circuit, comprising:
- a first logic-gate that receives a first address transition detection signal and a second address transition detection signal;
- a delay circuit that delays an output signal from the first logic-gate;
- a second logic-gate that receives output signals from the delay circuit and the first logic-gate and outputs a combined address transition detection signal;
- and
- a logic circuit that receives the combined address transition detection signal, a first signal and a second signal, and outputs a write control signal.
A method of operating a write control driver circuit, comprising:
- logically processing first and second address transition detection signals to generate a first signal;
- delaying the first signal;
- logically processing the delayed first signal and the first signal to output a combined address transition detection signal;
- logically processing a write enable signal and chip selection signal to generate a write driver signal;
- logically processing the combined address transition detection signal, the write driver signal and a coding signal to output a write control signal that is not controlled by the first and second address transition detection signals.
Dependencies are inferred from the claim text.