US 5,966,341 AGranted

Semiconductor memory

AssigneesHitachi, Ltd., Hitachi Device Engineering Co., Ltd.

InventorsTsugio Takahashi, Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura

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Abstract

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Claims9

Dependent claims

A semiconductor memory comprising:

a plurality of first regions arranged in lattice fashion, each of which corresponds to a memory array including a plurality of main word lines extending in a first direction, a plurality of sets of sub-word lines extending in said first direction, a plurality of pairs of data lines extending in a second direction perpendicular to said first direction and a plurality of memory cells, each of which is coupled to a corresponding one of said plurality of sub-word lines and a corresponding one of said data lines, one of said plurality of main word lines being allotted to one of said plurality of sets of sub-word lines;
a plurality of second regions, each of which is arranged alternately with each of said first regions arranged along said first direction and each of which includes sub-word line drivers connected to said sub-word lines;
a plurality of third regions, each of which is arranged alternately with each of said first regions arranged along said second direction and each of which includes sense amplifiers connected to said data lines;
and
a plurality of fourth regions, each of which is arranged alternately with each of said third regions arranged along said first direction,
wherein each of said plurality of main word lines extends through one or more of said first regions arranged along said first direction;
wherein said semiconductor memory further includes:
a plurality of pairs of sub-common data lines, each of which extends through said third regions arranged along said first direction;
first switching circuits formed in said third regions and connected interposingly between said plurality of pairs of data lines and a corresponding one of said pairs of sub-common data lines;
a plurality of pairs of main-common data lines, each of which extends through one or more of second regions arranged along said second direction;
and
second switching circuits formed in said fourth regions and connected interposingly between a corresponding one of said pairs of main-common data lines and a corresponding one of said pairs of sub-common data lines.

9 more elements

A semiconductor memory comprising:

a first region extending in a first direction;
a second region extending in said first direction and in parallel with said first region;
a third region extending in a second direction perpendicular to said first direction;
a fourth region formed as a rectangle, two sides of which are contiguous to said first region and said third region, respectively;
and
a fifth region formed as a rectangle, three sides of which are contiguous to said first region, said second region and said third region, respectively;
wherein said third region includes a pair of main common data lines extending in said second direction,
wherein said fourth region includes a first memory array having a plurality of first main word lines extending in said first direction, a plurality of sets of first sub-word lines extending in said first direction, a plurality of pairs of first data lines extending in said second direction and a plurality of first dynamic memory cells, each of which is coupled to a corresponding one of said plurality of first sub-word lines, each of said sets of first sub-word lines corresponding to one of said plurality of first main word lines,
wherein said fifth region includes a second memory array having a plurality of second main word lines extending in said first direction, a plurality of sets of second sub-word lines extending in said first direction, a plurality of pairs of second data lines extending in said second direction and a plurality of second dynamic memory cells, each of which is coupled to a corresponding one of said plurality of second sub-word lines, each of said sets of second sub-word lines corresponding to one of said plurality of second main word lines,
wherein said first region includes:
(1) a pair of first sub-common data lines extending in said first direction,
(2) first sense amplifiers connected to said plurality of pairs of first data lines and
(3) first switching circuits connected interposingly between said plurality of pairs of first data lines and said pair of first sub-common data lines,
wherein said second region includes:
(1) a pair of second sub-common data lines extending in said first direction,
(2) second sense amplifiers connected to said plurality of pairs of second data lines, and
(3) second switching circuits connected interposingly between said plurality of pairs of second data lines and said pair of second sub-common data lines,
wherein said first region and said third region intersect in a first crossing area including:
(1) a third switching circuit connected interposingly between said pair of main common data lines,
(2) a fourth switching circuit which provides said first sense amplifiers with a first positive power supply voltage, and
(3) a fifth switching circuit which provides said first sense amplifiers with a second positive power supply voltage lower than said first positive power supply voltage, and
wherein said second region and said third region intersect in a second crossing area including:
(1) a sixth switching circuit connected interposingly between said pair of main common data lines,
(2) a seventh switching circuit which provides said second sense amplifiers with said first positive power supply voltage, and
(3) an eighth switching circuit which provides said second sense amplifiers with said second positive power supply voltage.

22 more elements

A semiconductor memory comprising:

a first region extending in a first direction;
a second region extending in said first direction and in parallel with said first region;
a third region extending in a second direction perpendicular to said first direction;
a fourth region formed as a rectangle, two sides of which are contiguous to said first region and said third region, respectively;
and
a fifth region formed as a rectangle, three sides of which are contiguous to said first region, said second region and said third region, respectively;
wherein said third region includes a pair of main common data lines extending in said second direction,
wherein said fourth region includes a first memory array having a plurality of first main word lines extending in said first direction, a plurality of sets of first sub-word lines extending in said first direction, a plurality of pairs of first data lines extending in said second direction and a plurality of first dynamic memory cells, each of which is coupled to a corresponding one of said plurality of first sub-word lines, each of said sets of first sub-word lines corresponding to one of said plurality of first main word lines,
wherein said fifth region includes a second memory array having a plurality of second main word lines extending in said first direction, a plurality of sets of second sub-word lines extending in said first direction, a plurality of pairs of second data lines extending in said second direction and a plurality of second dynamic memory cells, each of which is coupled to a corresponding one of said plurality of second sub-word lines, each of said sets of second sub-word lines corresponding to one of said plurality of second main word lines,
wherein said first region includes:
(1) a pair of first sub-common data lines extending in said first direction,
(2) first sense amplifiers connected to said plurality of pairs of first data lines and
(3) first switching circuits connected interposingly between said plurality of pairs of first data lines and said pair of first sub-common data lines,
wherein said second region includes:
(1) a pair of second sub-common data lines extending in said first direction,
(2) second sense amplifiers connected to said plurality of pairs of second data lines, and
(3) second switching circuits connected interposingly between said plurality of pairs of second data lines and said pair of second sub-common data lines,
wherein said first region and said third region intersect in a first crossing area including a third switching circuit connected interposingly between said pair of first sub-common data lines and said pair of main common data lines,
wherein said second region and said third region intersect in a second crossing area including a fourth switching circuit connected interposingly between said pair of second sub-common data lines and said pair of main common data lines, and
wherein each of said first and second sub-word line drivers include:
(1) a first PMOS transistor having a gate connected to a corresponding one of said main word lines, a drain connected to a corresponding one of said sub-word lines and a source receiving a first signal,
(2) a first NMOS transistor having a gate connected to the gate of said first PMOS transistor, a drain connected to the drain of said first PMOS transistor and a source connected to a ground potential, and
(3) a second NMOS transistor having a drain connected to the drain of said first NMOS transistor, a source connected to said ground potential and a gate receiving a second signal, said first and second signals being complementary signals.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/982,398Filed 2 Dec 1997 · continuation
Priority: JP 6-33495020 Dec 1994
Granted: 12 Oct 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
G11C 7/10
Arrangements for writing information into, or reading information out from, a digital store: input/output [I/O] data interface arrangements, e.g.…
G11C 11/408
For memory cells of the field-effect type: address circuits
G11C 11/4096
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Family

Serial574,104Parent of this continuation · filed 20 Dec 1995
Serial779,835Parent of this continuation · filed 7 Jan 1997
US 5,777,927 AParent of this continuation
US 5,604,697 AParent of this continuation
US 5,966,341 AThis patent

From the US filing history. Foreign family members aren’t listed.