Semiconductor memory device having hierarchical word line structure

A semiconductor memory device comprising:

• at least one row block having a plurality of memory blocks each having a plurality of memory cells arranged in rows and columns, said plurality of memory blocks in said at least one row block being aligned in a row direction;
• a plurality of main word lines extending in said row direction over said plurality of memory blocks, and arranged corresponding to the respective rows in each of said plurality of memory blocks;
• a plurality of sub-word lines arranged within each of said plurality of memory blocks and corresponding to the rows in said each of the memory blocks, each of the sub-word lines being connected to the memory cells in a corresponding row;
• a plurality of global data lines arranged corresponding to said memory blocks respectively and extending in a column direction, for transmitting data to and from corresponding memory blocks when the corresponding memory blocks are selected;
• a plurality of power source lines arranged corresponding to the memory blocks and extending in said column direction, for transmitting a predetermined voltage;
• at least one conductive line arranged between a global data line of said plurality of global data lines and a corresponding power source line of said plurality of sower source lines, and
• a plurality of sub-decoders arranged corresponding to the memory blocks and corresponding to the respective rows in corresponding memory blocks, each for transmitting the predetermined voltage on a corresponding power source line onto a corresponding sub-word line in accordance with a decode signal and a signal signal on a corresponding main word line.