Programmable/reprogrammable fuse

A reprogrammable single row array comprising:

• an array of cells arranged in a matrix consisting of a single row and a plurality of columns of said cells;
• a multi-stage reprogrammable fuse arrangement controlling said cells positioned along one of said columns of said array of cells;
• and
• a multi-stage reprogrammable fuse arrangement controlling said cells positioned along said single row of said array of cells.

A reprogrammable logic or memory arrangement comprising:

• a reprogrammable fuse arrangement comprising:
• a plurality of fuse links provided each with an output;
• and
• a plurality of cascaded exclusive-or gates, wherein a first one of said exclusive-or gates is connected to the output of two fuse links of said plurality of fuse links, and each remaining exclusive-or gate from said plurality of exclusive-or gates has a first input connected to the output of a previous one of said exclusive-or gates and a second input connected to an unused one of said plurality of fuse links;
• a logic or memory block having a plurality of inputs and one output;
• and
• a switching gate provided with two inputs, one of said inputs being connected to said output of said logic or memory block, and the second input of said switching gate being connected to the last output of said exclusive-or gate of said reprogrammable fuse arrangement.

A reprogrammable logic or memory arrangement comprising:

• a reprogrammable fuse arrangement comprising:
• a plurality of fuse links provided each with an output;
• and
• a plurality of cascaded exclusive-or gates, wherein a first one of said exclusive-or gates is connected to the output of two fuse links of said plurality of fuse links, and each remaining exclusive-or gate from said plurality of exclusive-or gates has a first input connected to the output of a previous one of said exclusive-or gates and a second input connected to an unused one of said plurality of fuse links;
• a logic or memory block having a plurality of inputs and one output;
• and
• a plurality of switching gates coupled to said reprogrammable fuse arrangement and to said logic or memory block, wherein the output of said logic or memory block alternatively switches between a normal state of said logic or memory block and a high-impedance logic state.

A method for reprogramming a fuse arrangement comprising the steps of:

• providing two fuse links, each link having at least one terminal port;
• providing an exclusive-or gate connected to said at least one terminal port of each of said two fuse links;
• and
• successively blowing both of said two fuse links.

A method of reprogramming a multi-stage fuse arrangement comprising the steps of:

• providing a plurality of fuse links provided each with an output;
• providing a plurality of cascaded exclusive-or gates, wherein a first one of said exclusive-or gates is connected to the output of two fuse links of said plurality of fuse links, and each remaining exclusive-or gate from said plurality of exclusive-or gates has a first input connected to the output of a previous one of said exclusive-or gates and a second input connected to an unused one of said fuse links;
• and
• successively blowing said plurality of fuse links.