Dram with new I/O data path configuration

An integrated circuit comprising:

• a plurality of memory arrays arranged in a line extending from left to right, each memory array comprising a plurality of columns of memory cells, the memory arrays including two end memory arrays, one of the end memory arrays being a left end memory array and the other one of the end memory arrays being a right end memory array;
• a column decoding and amplifier circuit between every two adjacent memory arrays, the column decoding and amplifier circuit comprising sense amplifier circuitry for amplifying signals from columns of the adjacent arrays, the column decoding and amplifier circuit being for selecting 1 column from N columns of the adjacent arrays and for providing an amplified signal representing data from the selected column, where N is a predetermined number;
• a left end column decoding and amplifier circuit on the left of the left end memory array, the left end column decoding and amplifier circuit comprising sense amplifier circuitry for amplifying signals from columns of the left end memory array, the left end column decoding and amplifier circuit being for selecting 1 column from N/2 columns of the left end memory array and for providing an amplified signal representing data from the selected column;
• a right end column decoding and amplifier circuit on the right of the right end memory array, the right end column decoding and amplifier circuit comprising sense amplifier circuitry for amplifying signals from columns of the right end memory array, the right end column decoding and amplifier circuit being for selecting 1 column from N/2 columns of the right end memory array and for providing an amplified signal representing data from the selected column;
• one sense amplifier for each of said column decoding and amplifier circuits between adjacent memory arrays, the sense amplifier being for further amplifying the amplified signal provided by the respective column decoding and amplifier circuit and for providing a further amplified signal representing data from the column selected from the N columns of the respective adjacent memory arrays;
• a first sense amplifier for further amplifying the amplified signal provided by the left column decoding and amplifier circuit and for providing a further amplified signal representing data from the column selected from the N/2 columns of the left memory array;
• a second sense amplifier for further amplifying the amplified signal provided by the right column decoding and amplifier circuit and for providing a further amplified signal representing data from the column selected from the N/2 columns of the right memory array;
• and
• a node for receiving the further amplified signals from the first or the second sense amplifier in response to selection of the right end memory array or the left end memory array, signal on the node thus representing data from 1 column out of N columns of the left and right memory arrays, the N columns consisting of the N/2 columns of the left memory array and the N/2 columns of the right memory array.