Floating gate memory cell array allowing cell-by-cell erasure
AssigneeSanyo Electric Co., Ltd.
InventorYoh Takano
Life of this patent
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Abstract
A non-volatile semiconductor memory device includes a plurality of memory cells. Each of the plurality of memory cells has a control gate, a source, a drain and a floating gate for storing charges. The floating gate is preferably capacitively coupled to at least one of the source and the drain. The memory device also includes a control circuit for controlling voltages that are respectively applied to the control gate, the source and the drain in order to execute an erasure operation of at least one memory cell in a "memory cell-by-memory cell" format.
Claims25
A non-volatile semiconductor memory device comprising:
- an array of split gate memory cells, each split gate memory cell having a control gate, a source, a drain and a floating gate for storing charges, said floating gate being capacitively coupled to at least one of said source and said drain;
- a plurality of word lines respectively connected to said control gates of said array of split gate memory cells on a per row basis;
- a plurality of bit lines respectively connected to said drains of said array of split gate memory cells on a per column basis;
- and
- a control circuit for controlling voltages to be respectively applied to said control gates, said sources and said drains to execute erasure of said split gate memory cells in a cell-by-cell manner, wherein in a bit erase mode, said control circuit applies a first predetermined voltage to a bit line connected to said drain of a selected split gate memory cell, and a second predetermined voltage that is different from the first predetermined voltage to bit lines connected to said drains of nonselected split gate memory cells to suppress flow of Fowler-Nordheim tunnel currents between said floating gates and said control gates of the nonselected split gate memory cells.
A non-volatile semiconductor memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- an array of split gate memory cells that are selectable by said plurality of word lines and said plurality of bit lines, each split gate memory cell having a control gate connected to an associated one of said plurality of word lines, a drain connected to an associated one of said plurality of bit lines, a source, and a floating gate, said floating gate being capacitively coupled to said drain;
- and
- a control circuit for controlling voltages that are respectively applied to said word lines, said bit lines and said sources in a memory cell-by-memory cell manner in order to execute erasure of a single, selected split gate memory cell, wherein said control circuit applies a sufficient voltage for inducing a Fowler-Nordheim tunnel current to flow into said floating gate of the selected split gate memory cell.
Dependencies are inferred from the claim text.