Method and apparatus for measuring the threshold voltage of flash EEPROM memory cells being applied a variable control gate bias

In a semiconductor integrated circuit memory device having a threshold measurement circuitry for measuring the value of the threshold voltage of a memory core cell in an array of flash EEPROM memory core cells, said measurement circuitry comprising in combination:

• a cell matrix having a plurality of memory cells arranged in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate array core transistor having its control gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source and substrate connected to a ground potential;
• each of said array core transistors having a corresponding array threshold voltage which is to be measured;
• a reference current at a constant value being generated by a reference cell transistor having a fixed bias condition and a fixed threshold voltage so that the relationship of the bias voltage applied to its gate and said fixed threshold voltage is linear;
• a control gate bias voltage applied to the gate of said array core transistor having the array threshold voltage which is to be measured being varied continuously;
• and
• means for comparing said varied control gate bias voltage and said reference current level and for generating a high logic when said varied control gate bias voltage produces a core cell current which is greater than said reference current level to obtain immediately the value of the threshold voltage of the array core transistor.