Nonvolatile semiconductor memory device having a program area
AssigneeNEC Corporation
InventorHiroyuki Kobatake
Life of this patent
Estimating the term…
Abstract
A flash EEPROM includes a an array of nonvolatile memory cells each having a cell transistor of a double gate structure and a program area for the floating gate of the cell transistor. The flash EEPROM is subjected to programming, flash erasing and read mode, each of a byte by byte mode. The flash EEPROM includes first through third selection transistors, for disconnecting the source, drain and control gate of the selected cell transistor from those of the unselected cell transistors in a byte for suppressing a disturbance between cell transistors.
Claims8
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate, a memory cell array including a plurality of nonvolatile memory cells each including a cell transistor having source and drain regions on said semiconductor substrate, and a floating gate and a control gate each disposed in association with said source and drain regions, and a program area formed on a portion of said semiconductor substrate underlying a part of said floating gate;
- a plurality of word lines each disposed for a corresponding row of said nonvolatile memory cells;
- a plurality of bit lines each disposed for a corresponding column of said nonvolatile memory cells;
- a first selection transistor disposed for each group of said cell transistors for responding to selection of a corresponding one of said word lines to apply a first fixed voltage to the drains and the control gates of a corresponding group of said cell transistors;
- a second selection transistor for responding to the selection of the corresponding one of said word lines to apply a second fixed voltage to said program area;
- and a third selection transistor disposed for each said cell transistor for responding to the selection of the corresponding one of said word lines to apply said first fixed voltage to the source of said cell transistor.
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate, a memory cell array including a plurality of nonvolatile memory cells each including a cell transistor having source and drain regions on said semiconductor substrate, and a floating gate and a control gate each disposed in association with said source and drain regions, and a program area formed on a portion of said semiconductor substrate underlying a part of said floating gate;
- a plurality of word lines each disposed for a corresponding row of said nonvolatile memory cells;
- a plurality of bit lines each disposed for a corresponding column of said nonvolatile memory cells;
- a first selection transistor disposed for each group of said cell transistors for responding to selection of a corresponding one of said word lines to apply a first fixed voltage to the drains of a corresponding group of said cell transistors;
- a second selection transistor disposed for the each group of said cell transistors for responding to the selection of the corresponding one of said word lines to apply a second fixed voltage to the control gates of said group of said cell transistors, a third selection transistor disposed for each said cell transistor for responding to the selection of a corresponding one of said word lines to apply a third fixed voltage to said program area, and a fourth selection transistor disposed for the corresponding one of said cell transistor to apply said second voltage to the source of said cell transistor.
Dependencies are inferred from the claim text.