On-off current ratio improving circuit for flat-cell array

A selection circuit for a memory device, comprising:

• a memory array having a plurality of cells with a matrix form of rows and columns;
• a plurality of conductive contacts to transmit data from the memory array, wherein a selected conductive contact transmits selected data from a selected cell in the memory array;
• a first selection unit coupled to the memory array, the contacts and a fixed voltage terminal directly connected to an external prescribed voltage to select a pair of cells including the selected cell in a row of the memory array;
• a second selection unit connected to a first set of columns in the memory array and the first selection unit;
• and
• a third selection unit connected to a second set of columns in the memory array and the first selection unit, wherein the second and third selection units select the selected cell from the pair of cells, wherein each conductive contact is a metal contact connected to a plurality of metal bit lines, wherein the external prescribed voltage is ground, and wherein the remaining conductive contacts are coupled to the ground using the fixed terminal to electrically isolate the selected contact in the memory array.

A selection circuit for a memory device, comprising:

• a memory array having a plurality of cells;
• a plurality of conductive contacts to transmit data from the memory array, wherein a selected conductive contact transmits selected data from a selected cell in the memory array, wherein each conductive contact is a metal contact connected to a plurality of metal bit lines in the memory array;
• an externally connected voltage terminal;
• first and second selection units to form a connection path between the selected contact, the selected cell and the externally connected voltage terminal, wherein the first and second selection units connect the remaining conductive contacts to the externally connected voltage terminal to electrically isolate the selected contact in the memory array.