Nonvolatile semiconductor memory equipped with single bit and multi-bit cells
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-wook Park, Kang-deok Seo
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory having a single bit cell array and a multi-bit cell array formed on a substrate of the memory is provided. The memory includes a plurality of memory blocks that correspond to the input/output lines and is divided into a plurality of pages. A plurality of bit lines of the single bit cell array is coupled to a plurality of page buffers. The multi-bit cell array includes a plurality of memory blocks in which one of the blocks corresponds to a plurality of the input/output lines and is divided into a plurality of pages. A plurality of bit lines of the multi-bit cell array is coupled to a plurality of page buffers, A timing controller arranges the processing operations in the two arrays.
Claims11
A nonvolatile memory comprising:
- a plurality of input/output lines;
- a single bit cell array having a plurality of single-bit cell bit lines and a plurality of single-bit memory blocks, each single-bit memory block being coupled to an input/output line and being divided into a plurality of single-bit cell pages having a plurality of single-bit cell page buffers, the plurality of single-bit cell bit lines being coupled to the plurality of single-bit cell page buffers;
- and
- a multi-bit cell array having a plurality of multi-bit cell bit lines and a plurality of multi-bit cell memory blocks, each multi-bit cell memory block being coupled to one or more input/output lines and being divided into a plurality of multi-bit cell pages having a plurality of multi-bit cell page buffers, the plurality of multi-bit cell bit lines being coupled to the plurality of multi-bit cell page buffers.
A nonvolatile memory, comprising:
- a plurality of input/output lines;
- a single bit cell array having a plurality of single-bit cell bit lines and a plurality of single-bit cell memory blocks, each single-bit cell memory block coupled to a respective input/output line and being divided into a plurality of single-bit cell pages having a plurality of single-bit cell page buffers, the plurality of single-bit cell bit lines being coupled to the plurality of single-bit cell page buffers;
- and
- a multi-bit cell array having a plurality of multi-bit cell bit lines and a plurality of multi-bit cell memory blocks, each multi-bit cell memory block coupled to at least one respective input/output lines and being divided into a plurality of multi-bit cell pages having a plurality of multi-bit cell page buffers, the plurality of multi-bit cell bit lines being coupled to the plurality of multi-bit cell page buffers;
- and
- a timing controller coupled to the single bit and multi bit cell arrays for generating control signals necessary to arrange processing operations in the plurality of single-bit and multi-bit page buffers.
A method for operating a nonvolatile memory, comprising the steps of:
- a row address detector receiving from a row address buffer a memory address which is located in one of a single bit cell array and a multi-bit cell array which are formed on a single substrate;
- the row address detector determining whether the address is in one of the single bit cell array and the multi-bit cell array;
- the row address detector processing a signal to one of a single bit timing controller and a multi-bit timing controller to access one of the single bit array and the multi-bit array.
Dependencies are inferred from the claim text.