SRAM structure having common bit line
AssigneeWinbond Electronics Corp.
InventorJowsoon Hsu
Life of this patent
Estimating the term…
Abstract
A static random access memory having a structure that allow two memory cells to use a common complementary bit line. With two memory cells using a common complementary bit line, the number of necessary bit lines will be reduce by one quarter. In other words, one quarter fewer metal lines are required. This has the effect of lowering the packing density of metal lines, or increasing the product yield and the number of memory cells that can be packed within the same wafer area.
Claims9
A static random access memory structure that uses a common bit line, comprising:
- a first bit line;
- a second bit line;
- a common complementary bit line;
- a first memory cell with one end coupled to the first bit line and the other end coupled to the common complementary bit line;
- a second memory cell with one end coupled to the second bit line and the other end coupled to the common complementary bit line;
- a first Y-select signal controlling the first bit line;
- and
- a second Y-select signal controlling the second bit line;
- wherein the common complementary bit line is controlled jointly by the first Y-select signal and the second Y-select signal.
A static random access memory structure that uses a common bit line, comprising:
- a first bit line;
- a second bit line;
- a common complementary bit line;
- a first memory cell with one end coupled to the first bit line and the other end coupled to the common complementary bit line;
- a second memory cell with one end coupled to the second bit line and the other end coupled to the common complementary bit line;
- a first Y-select signal;
- a first complementary Y-select signal, wherein the first Y-select signal and the first complementary Y-select signal together control the first bit line;
- a second Y-select signal;
- a second complementary Y-select signal, wherein the second Y-select signal and the second complementary Y-select signal together control the first bit line;
- an OR gate with the first Y-select signal line coupled to a first input terminal of the OR gate, and the second Y-select signal line coupled to a second input terminal of the OR gate;
- and
- an AND gate with the first complementary Y-select signal line coupled to a first input terminal of the AND gate, and the second complementary Y-select signal line coupled to a second input terminal of the AND gate;
- wherein the output terminal of the AND gate and the output terminal of the OR gate together control the common complementary bit line.
A static random access memory structure that uses a common bit line, comprising:
- a first complementary bit line;
- a second complementary bit line;
- a common bit line;
- a first memory cell with one end coupled to the first complementary bit line and the other end coupled to the common bit line;
- a second memory cell with one end coupled to the second complementary bit line and the other end coupled to the common bit line;
- a first Y-select signal controlling the first complementary bit line;
- and
- a second Y-select signal controlling the second complementary bit line;
- wherein the common bit line is controlled jointly by the first Y-select signal and the second Y-select signal.
Dependencies are inferred from the claim text.