Static memory device allowing correct data reading
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHirotoshi Sato
Life of this patent
Estimating the term…
Abstract
A memory cell includes driver transistors constituting a cross coupled type flipflop, access transistors driven in response to a signal potential on a word line, and bipolar transistors for connecting the memory cell to bit lines. For the bit lines, a read load circuit including diode coupled p channel MOS transistors and cross coupled p channel MOS transistors is provided, which supplies current when activated, and latches the bit line potentials after a prescribed time period. Stable data reading at high speed with low current consumption even under low power supply voltage is ensured, without causing data destruction.
Claims20
A semiconductor memory device, comprising:
- a word line;
- a pair of bit lines arranged crossing said word line;
- a memory cell arranged corresponding to a crossing portion between said word line and said pair of bit lines, said memory cell including a cross coupled type flipflop for storing complementary data at a pair of storage nodes, a pair of bipolar transistors provided corresponding to said pair of bit lines, respectively and each having one conduction node connected to a corresponding bit line, and a pair of access transistors responsive to a signal potential on said word line for coupling the pair of storage nodes of said cross coupled type flipflop to base electrodes of said pair of bipolar transistors, respectively;
- and
- a read load circuit coupled to said pair of bit lines for reading and amplifying data of said memory cell to said pair of bit lines at a time of data reading, said read load circuit including a pair of diode elements connected to said pair of bit lines respectively, a pair of cross coupled transistors for differentially amplifying and latching potentials of said pair of bit lines, a first switching transistor for electrically connecting said pair of diode elements to a power source supplying a first power supply voltage, and a second switching transistor for electrically connecting said pair of cross coupled transistors to said power source.
A semiconductor memory device, comprising:
- a plurality of bit line pairs;
- a plurality of word lines arranged crossing said plurality of bit line pairs;
- a plurality of memory cells provided corresponding to crossing portions between said plurality of bit line pairs and said plurality of word lines, and each storing data, each of said plurality of memory cells including a cross coupled type flipflop for storing complementary data at a pair of storage nodes, a pair of bipolar transistors provided corresponding to the bit lines of respective bit line pairs and each having one conduction node connected to a corresponding bit line, and a pair of access transistor responsive to a signal potential of a corresponding word line for coupling the pair of storage nodes of said cross coupled type flipflop to base electrodes of said pair of bipolar transistors;
- bit line selecting means for selecting, in accordance with a bit line selection signal, a bit line pair designated by said bit line selection signal out of said plurality of bit line pairs;
- and
- read load means coupled to the bit line pair selected by said bit line selecting means, for reading and amplifying data of a selected memory cell to said selected bit line pair, said read load means including at least one pair of read load bus lines coupled to said selected bit line pair, a pair of diode elements respectively connected to said pair of read load bus lines, a pair of cross coupled transistors for differentially amplifying and latching signal potentials on said pair of read load bus lines, a first switching transistor for electrically connecting said pair of diode elements to a power source supplying a first power supply voltage, and a second switching transistor for electrically connecting said pair of cross coupled transistors to said power source.
Dependencies are inferred from the claim text.