Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines

A semiconductor memory having a plurality of row and columns, comprising:

• at least one sense amplifier in each column;
• a master bit line operatively coupled to the sense amplifier;
• a plurality of local bit lines disposed in each column, each coupled to memory cells and vertically spaced from the master bit line in the column and selectively coupled to the sense amplifier, said plurality of local bit lines including a near side local bit line selectively coupled to the sense amplifier via a first switch couple therebetween, and at least one far side local bit line selectively coupled to the sense amplifier via the master bit line and a second switch coupled between the master bit line and the sense amplifier;
• wherein the near side local bit line is coupled to a larger number of memory cells and has a longer length than any of said at least one far side local bit line.

A semiconductor memory having a plurality of rows and columns, comprising:

• at least one sense amplifier in each column;
• a master bit line operatively coupled to the sense amplifier;
• a plurality of local bit lines disposed in each column, each coupled to memory cells and vertically spaced from the master bit line in the column and selectively coupled to the sense amplifier, said plurality of local bit lines including a near side local bit line selectively coupled to the sense amplifier via a first switch coupled therebetween, and a plurality of far side local bit lines, each selectively coupled to the sense amplifier via the master bit line and a plurality of additional switches;
• said plurality of additional switches comprising a second switch coupled between the master bit line and the sense amplifier and a local bit line switch coupled between each far side local bit line and the master bit line;
• wherein the near side local bit line is coupled to a larger number of memory cells than each of the far side local bit lines.