An array substrate for a display device comprising a plurality of scanning line being disposed on a substrate and including a gate electrode region, storage capacitor lines extending in substantially parallel with said scanning lines, a thin film transistor having a first insulator film on said storage capacitor lines, a semiconductor film disposed on at least said gate electrode region, and source and drain electrodes electrically connected to said semiconductor film, a second insulator film on said thin film transistor, a signal line electrically connected to the drain electrode through said second insulator film and substantially perpendicularly intersecting said scanning lines, and a pixel electrode electrically connected to the source electrode through said second insulator film, wherein
- each said storage capacitor line includes a bundling lead member extending in a direction substantially perpendicular to each of said storage capacitor lines with the first and second insulator films being laid therebetween, and
- each of said storage capacitor lines and said bundling lead member include a storage capacitor connecting section electrically connected through a conductive layer.