Optimized FIFO memory
AssigneeCirrus Logic, Inc.
InventorPatrick A. Harkin
Life of this patent
Estimating the term…
Abstract
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.
Claims15
A graphics processor having an internal storage unit for rendering graphics primitives, the graphics processor comprising:
- a bus interface unit for fetching display list instructions representing graphics primitives from an external memory source, said bus interface unit including bus-mastering circuitry to allow the graphics processor to bus-master an external system bus coupled to the graphics processor, said bus interface unit further comprising an address decoding means for decoding commands to determine whether to write commands and data to the internal storage unit;
- an internal storage unit coupled to the bus interface unit for internally storing pre-fetched graphics primitive data to be processed in the graphics processor, said internal storage unit comprising a plurality of registers for storing commands and data from said pre-fetched graphics primitive data, wherein the plurality of registers are First-In-First-Out (FIFO) registers and wherein data first received in the plurality of registers is first written out of the plurality of registers;
- an execution unit coupled to the bus interface unit and the internal storage unit to process the graphics primitive data;
- a bypass logic device coupled to the bus interface unit to selectively pass the graphics primitive data to the internal storage unit and the execution unit wherein if the bus interface unit detects an ongoing processing of commands and data stored in the internal storage unit, any incoming fetched graphics primitive data in the graphics processor are written directly to the execution unit;
- and
- a polygon engine for rendering graphics objects representing the graphics primitive data fetched from the external memory source.
A computer system comprising:
- a system bus for communicating data and commands;
- a host processor coupled to the system bus for processing the commands and data, the processor generating a display list of graphics primitive parameter data for graphics primitives;
- a system memory coupled to the system bus for storing the display list of graphics primitive parameter data;
- and
- a graphics processor coupled to the system bus, said graphics processor comprising:
- a bus interface unit for fetching the display list of graphics primitive parameter data from the system memory, the bus interface unit providing the graphics processor with bus-mastering capabilities to bus-master the system bus, said bus interface unit further comprising an address decoding means for decoding commands to determine whether to write commands and data to the internal storage unit;
- an internal storage unit coupled to the bus interface unit for storing the fetched display list of graphics primitive parameter data from the system memory, said internal storage unit comprising a plurality of registers for storing commands and data from said pre-fetched graphics primitive data, wherein the plurality of registers are First-In-First-Out (FIFO) registers and wherein data first received in the plurality of registers is first written out of the plurality of registers;
- an execution unit coupled to the bus interface unit and the internal storage unit to process the graphics primitive data;
- a bypass logic device coupled to the bus interface unit to selectively pass the graphics primitive data to the internal storage unit and the execution unit wherein if the bus interface unit detects an ongoing processing of commands and data stored in the internal storage unit, any incoming fetched graphics primitive data in the graphics processor are written directly to the execution unit;
- and
- a polygon engine for rendering graphics objects representing the graphics primitive data fetched from the system memory.
A graphics primitive storage bypass system for selectively storing graphics primitive parameter data internally in a graphics processor comprising:
- an address command register disposed within a graphics primitive bus interface unit;
- a decoding device coupled to the address command register to receive and decode the commands provided in the graphics primitive parameter data;
- a bypass device coupled to the decoding circuit to selectively determine where to write the pre-fetched commands internally in the graphics processor;
- and
- a adder device coupled to the bypass device for counting the number of storage locations in the internal storage unit storing commands pre-fetched to be processed in the graphics processor, said bypass device being selectively operable for detecting when ongoing processing of the stored commands is continuing, said graphics primitive storage bypass system being selectively operable for directly writing incoming pre-fetched graphics primitive parameter data to an execution unit of said graphics processor when ongoing processing of commands and data stored in said internal storage unit is detected.
A method of optimizing graphics primitive parameter data storage internally in a graphics processor, said method comprising:
- (a) generating a display list of graphics primitive parameter data in a host processor;
- (b) prefetching the graphics primitive parameter data for processing in the graphics processor;
- (c) selectively storing commands in the display list of graphics primitive parameter data in an internal storage unit of the graphics processor;
- (d) detecting when ongoing processing of the stored commands is continuing;
- and
- (e) directly writing incoming prefetched graphics primitive parameter data to an execution unit of said graphics processor when ongoing processing of commands and data stored in said internal storage unit is detected.
Dependencies are inferred from the claim text.