Pseudo-synchronizing signal generator for use in digital image processing apparatus

A circuit for receiving a horizontal synchronizing signal from an external source, a program data signal and a dot clock signal, said circuit generating a pseudo-synchronizing signal for use in a digital image processing apparatus, said circuit comprising:

• a pulse generating circuit receiving said synchronizing signal and said dot clock for generating a pulse of predetermined width in sync with a rising edge of said dot clock;
• said pulse generating circuit comprising:
• first and second flip-flops, both having a clear terminal for resetting said first and second flip-flops in response to said horizontal synchronizing signal;
• a first AND gate disposed to receive said dot clock signal and a signal output from a Q terminal of said first flip-flop, said first AND gate generating a first logical product signal, said first logical product signal being applied to a clock input terminal of said first flip-flop;
• an inverter disposed to produce a inverted dot clock signal by inverting said dot clock signal;
• a second AND gate disposed to receive said inverted dot clock signal and a signal output from a Q terminal of said second flip-flop at its respective input terminals, said second AND gate generating a second logical product signal, said second logical product signal being applied to a clock input terminal of said second flip-flop;
• and
• an exclusive OR gate having a pair of input terminals disposed to receive a signal output from a Q terminal of said first flip-flop and a Q terminal of said second flip-flop, respectively, for generate said pulse of predetermined width;
• a counting controller receiving said program data signal, said pulse of predetermined width and a reset signal for generating a program data enable signal;
• a down counter receiving said dot clock signal and said program data enable signal, said down counter being disposed to be enabled by said program data enable signal for counting down from a preset counting value in response to said dot clock signal;
• a zero detector receiving a current count value of said down counter for detecting when said current count value equals zero, said zero detector simultaneously generating a disable signal and a first pseudo-synchronizing signal upon detection of said zero count value, said disable signal being applied to said down counter for disabling a counting operation;
• and
• means for receiving and selectively outputting one of said horizontal synchronizing signal and said first pseudo-synchronizing signal as a second pseudo-synchronizing signal in response to said program data signal.

A method for generating a pseudo-synchronizing signal, for use in a digital image processing apparatus, in response to the receipt of a synchronizing signal from an external source, a program data signal and a dot clock signal, said method comprising the steps of:

• generating a pulse of predetermined width in sync with a rising edge of said dot clock signal while receiving said synchronizing signal;
• generating a program data enable signal in response to said program data signal, said pulse of predetermined width and a reset signal;
• counting down from a preset counting value in response to said dot clock signal in response to said dot clock signal and said program data enable signal;
• detecting when a current count value of said step of counting down equals zero;
• simultaneously generating a disable signal and a first pseudo-synchronizing signal upon detection of a zero count value, said disable signal being utilized for disabling said step of counting down;
• and
• selectively outputting one of said synchronizing signal and said first pseudo-synchronizing signal as a second pseudo-synchronizing signal in response to said program data signal.