Loading patent…
AssigneeSeiko Epson Corporation of Tokyo Japan
InventorsHo Dai Truong, Chong Ming Lin
Estimating the term…
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.
A programmable clock generator system for generating a plurality of clock signals having non-overlapping edges, comprising:
A method for adjusting a non-overlapping edge time between a first and second clock signal utilizing a programmable clock generator, the programmable clock generator including first and second delay paths configured to receive the first and second clock signal, respectively, each of the first and second delay paths including a plurality of delay lines, each of the plurality of delay lines including one or more delay elements and one or more bypass circuits, the method comprising the steps of:
Dependencies are inferred from the claim text.