High voltage tolerable input buffer

An input pad buffer circuit for an integrated circuit having a first voltage supply for providing a first supply voltage and a second voltage supply for providing a second supply voltage, the first supply voltage being greater than the second supply voltage, the input pad buffer circuit comprising:

• an input pad of the integrated circuit for receiving a digital input signal which varies between a logic high state and a logic low state, wherein the input signal has a voltage approximately equal to the first supply voltage when in the logic high state, and wherein the input signal has a voltage approximately equal to the second supply voltage when in the logic low state;
• an output terminal;
• a first n-channel field effect transistor (FET) having a drain region coupled to the first voltage supply, a source region coupled to the output terminal, and a gate electrode coupled to the input pad;
• a second n-channel FET having a drain region coupled to the source region of the first n-channel transistor, a source region connected to the second voltage supply, and a gate electrode;
• a third n-channel FET having a source region connected to the second voltage supply, a drain region, and a gate electrode coupled to the gate electrode of the second n-channel FET and to the drain region of the third n-channel FET;
• and
• a fourth n-channel FET having a source region connected to the drain region of the third n-channel FET, a drain region coupled to the first voltage supply and a gate electrode coupled to receive a bias voltage which is less than the first supply voltage and greater than the second supply voltage.