BiCMOS transceiver (driver and receiver) for gigahertz operation
AssigneeNorthern Telecom Limited
InventorsMuhammad S. Elrabaa, Mohamed I. Elmasry, Duljit S. Malhi
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Abstract
Several low power, low voltage swing, BiCMOS circuits for used in high speed chip-to-chip communications are described. In particular a BiCMOS low voltage swing transceiver comprising a driver and a receiver with low on-chip power consumption is reported. Operating at 3.3.V, the universal transceiver can drive and receive low voltage swing signals with termination voltages ranging from 5V down to 2V, without using external reference voltages and at frequencies exceeding 1 GHz. On-chip power consumption is much lower than that of known CML/ECL type transceivers having comparable speeds.
Claims19
A transceiver for high speed chip to chip communications over a transmission line with termination voltage V.sub.T, comprising a driver circuit and a receiver circuit, wherein the receiver circuit comprises:
- an input buffer (UIB);
- means for generating a reference voltage (V.sub.ref);
- and load control means for generating first and second control voltages V1 and V2;
- the input buffer comprising an emitter coupled differential pair of first and second bipolar junction transistors (BJTs) coupled to a source follower stage comprising a plurality of pairs of PMOS transistors, the PMOS transistors providing a load means;
- an input signal means and the reference voltage V.sub.ref generating means being coupled respectively to the bases of the first and second of BJTs;
- the load control means being coupled to the gates of the PMOS transistors, for providing first and second control voltages V1 and V2 for biasing corresponding pairs of gates of the PMOS transistor pairs of the load means.
A transceiver comprising a receiver circuit and a driver circuit, wherein the driver comprises:
- current source means comprising a dynamically controlled biasing network for generating a control voltage V.sub.c from an input signal whereby the low value of an output current is near zero and the high value of an output current is independent of the voltage swing of the input signal, the dynamically controlled biasing network comprising a V.sub.BE multiplier having a first bipolar transistor Q1 biased by first resistor R and second resistor zR where z is the multiplication factor, wherein z is selected to provide a near zero tail current.
A transceiver comprising a receiver circuit and a driver circuit,
- the receiver circuit comprising an input buffer comprising an emitter coupled bipolar junction transistor pair, and source follower stage comprising a plurality of PMOS load devices, voltage generating means for providing a reference voltage and load control means for generating first and second control voltages for biasing the PMOS load devices whereby the first and second BJTs do not saturate;
- and
- the driver circuit comprising a current source means having a dynamically controlled biasing network.
A BiCMOS integrated circuit comprising a receiver circuit for a transceiver for high speed chip-to-chip communications over a transmission line with termination voltage V.sub.T, the receiver circuit comprising:
- the receiver circuit comprises:
- an input buffer (UIB);
- means for generating a reference voltage (V.sub.ref);
- and load control means for generating first and second control voltages V1 and V2;
- the UIB comprising an emitter coupled differential pair of first and second bipolar junction transistors (BJTs) coupled to a source follower stage comprising a plurality of pairs of PMOS transistors, the PMOS transistors providing a load means;
- an input signal means and the reference voltage V.sub.ref generating means being coupled respectively to the bases of the first and second of BJTs;
- the load control means being coupled to the gates of the PMOS transistors, first and second control voltages V1 and V2 for biasing corresponding pairs of gates of the PMOS transistor pairs of the load means.
An BiMOS integrated circuit comprising a driver circuit for a transceiver for high speed chip-to-chip communications, the driver circuit comprising:
- current source means comprising a dynamically controlled biasing network for generating a control voltage V.sub.c from an input signal whereby the low value of an output current is near zero and the high value of an output current is independent of the voltage swing of the input signal, the dynamically controlled biasing network comprising a V.sub.BE multiplier having a first bipolar transistor Q1 biased by first resistor R and second resistor zR where z is the multiplication factor, wherein z is selected to provide a near zero tail current.
Dependencies are inferred from the claim text.