US 5,966,031 AGranted

Output circuit for integrated circuit devices

AssigneeYahama Corporation

InventorYasuhiko Sekimoto

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Abstract

An output circuit for an integrated circuit device in which first and second power wirings are connected to a high-potential power terminal, third and fourth power wirings are connected to a low-potential power terminal, and a plurality of inverters are responsive, respectively, to a plurality of bit data signals, each being formed of P-channel and N-channel MOS transistors having drains thereof connected together, a junction of which forms an output terminal. First to fourth auxiliary transistors are provided for each of the inverters, which are connected, respectively, between the first power wiring and the source of the P-channel MOS transistor, between the second power wiring and the source of the P-channel MOS transistor, between the third power wiring and the source of the N-channel MOS transistor, and between the fourth power wiring and the source of the N-channel MOS transistor. First and second circuits are provided for each inverter and operable in response to one of the bit signals corresponding to each inverter to control the transistors ON and OFF states.

An output circuit for an integrated circuit device, comprising:

a first power terminal which is supplied with a high potential;
first and second power wirings connected to said first power terminal;
a second power terminal which is supplied with a low potential;
third and fourth power wirings connected to said second power terminal;
a plurality of inverters responsive, respectively, to a plurality of bit signals constituting a data signal, each of said inverters being formed of P-channel and N-channel MOS transistors having drains thereof connected together, a junction of which forms an output terminal;
first to fourth auxiliary transistors provided for each of said inverters and each having a source, said first auxiliary transistor being connected between said first power wiring and the source of said P-channel MOS transistor, said second auxiliary transistor being connected between said second power wiring and the source of said P-channel MOS transistor, said third auxiliary transistor being connected between said third power wiring and the source of said N-channel MOS transistor, and said fourth auxiliary transistor being connected between said fourth power wiring and the source of said N-channel MOS transistor;
a first circuit provided for said each of said inverters and operable in response to one of said bit signals corresponding to said each of said inverters, for controlling said third and fourth auxiliary transistors such that said third auxiliary transistor is in ON state during a first predetermined time period including timing of turning-on of said N-channel MOS transistor, and turned off after termination of said first predetermined period, and said fourth auxiliary transistor is turned on after the turning-off of said third auxiliary transistor;
and
a second circuit provided for said each of said inverters and operable in response to said one of said bit signals corresponding to said each of said inverters, for controlling said first and second auxiliary transistors such that said first auxiliary transistor is in ON state during a second predetermined time period including timing of turning-on of said P-channel MOS transistor, and turned off after termination of said second predetermined period, and said second auxiliary transistor is turned on after the turning-off of said first auxiliary transistor.

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Abstract

Claims3