Wafer level burn-in system
AssigneeW. L. Gore & Associates, Inc.
InventorsJohn J. Budnaitis, Jimmy Leong
Life of this patent
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Abstract
The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
Claims126
A device for burn-in screening of integrated circuits having a plurality of contact pads, comprising:
- a high planarity base unit having a low CTE or matched composite CTE base unit with a plurality of first and second terminals at a lower surface thereof, said second terminals connectable to a test signal generator and said first terminals coupled to a wafer level contact sheet;
- and
- a laminated wafer level contact sheet including a Z-axis conductive layer and a plurality of uniformly configured conductive bumps that register with contacts on a semiconductor wafer.
Dependencies are inferred from the claim text.