Electronic system with regulator, and method

An apparatus, comprising:

• first and second transistors serially coupled between first and second reference lines via an output node, said first transistor temporarily forwarding d.c. input current from said first reference line to said output node and said second transistor temporarily discharging capacitance between said output node and said second reference line;
• a consuming device coupled between said output node and said second reference line, said consuming device temporarily sinking a load current;
• a voltage sensor measuring a voltage between said output node and said second reference line and providing a measurement voltage;
• and
• first and second comparators for controlling said first and second transistors, respectively, said first and second comparators each receiving said measurement voltage, and said second comparator having an offset relative to said first comparator, wherein changes of said measurement voltage when said consuming device stops to sink said load current causes consecutively (a) said first transistor to become non-conductive and (b) said second transistor to become conductive so that said first transistor releases said output node before said second transistor pulls said output node to said second reference line.

A method of supplying a load current (I.sub.OUT) to a load while maintaining a load voltage whose amount is larger than or equal to a minimum output voltage (.vertline.V.sub.OUT .vertline..gtoreq..vertline.V.sub.OUT MIN .vertline.), said method comprising the steps of:

• (a) forwarding an input current (I.sub.IN) to said load current (I.sub.OUT) by a first transistor, thereby regulating the conduction of said first transistor by a first operational amplifier receiving a portion (.vertline.V.sub.M .vertline.) of said load voltage (.vertline.V.sub.OUT .vertline.);
• (b) monitoring said portion (.vertline.V.sub.M .vertline.) by a second operational amplifier which has an offset voltage (.vertline.V.sub.OS .vertline.);
• and
• (c) temporarily shorting said load voltage (.vertline.V.sub.OUT .vertline.) by a second transistor controlled by said second operational amplifier when said portion (.vertline.V.sub.M .vertline.) exceeds said offset voltage (.vertline.V.sub.OS .vertline.), said shorting being limited in time so that the load voltage satisfies the condition to be larger than or equal to said minimum output voltage (.vertline.V.sub.OUT .vertline..gtoreq..vertline.V.sub.OUT MIN .vertline.).