US 5,965,940 A · Intermetal dielectric planarization by metal features layout modification

Abstract

A technique is disclosed for general IC structures to modify the layout of electrically unisolated metal lines before patterning same so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer. Upon such standardization of metal line spacing, the intermetal dielectric will be planarized in a single process step of deposition. Circuit layout design modifications can be made by adding electrically isolated dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing between the metal lines and dummy metal features. As the nonstandard spacing between metal lines becomes standardized, an intermetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.

Claims22

Dependent claims

An integrated circuit structure comprising:

a substrate;
a plurality of electrically unisolated metal lines on said substrate each:
having the same height T.sub.MET and being parallel one with another;
and
being separated from the nearest of the other electrically unisolated metal lines;
n electrically isolated metal lines each:
having a width W.sub.met ;
and
being situated in the separation between the each electrically unisolated metal line and the nearest of the other electrically unisolated metal lines;
a dielectric layer having a thickness of T.sub.idl over:
said substrate;
said plurality of electrically unisolated metal lines;
and
said n electrically isolated metal lines;
wherein there is a separation S.sub.met between:
each electrically unisolated metal line and the nearest of one of:
another electrically unisolated metal line;
or
one of said electrically isolated metal lines;
each electrically isolated metal line and the nearest of one of:
another electrically isolated metal line;
or
one of said electrically unisolated metal lines;
wherein:
S.sub.met is not greater than (1.4(n+1)T.sub.idl +(n)W.sub.met) or twice T.sub.idl ;
and
n is a maximized whole number not greater than (S.sub.met -1.4T.sub.idl)/(1.4T.sub.idl +W.sub.met).

24 more elements

An integrated circuit structure comprising:

a substrate;
a plurality of electrically unisolated metal lines on said substrate each:
having the same height T.sub.MET and being parallel one with another;
and
being separated from the nearest of the other electrically unisolated metal lines;
n electrically isolated metal lines each:
having a width W.sub.met ;
and
being situated in the separation between the each electrically unisolated metal line and the nearest of the other electrically unisolated metal lines;
a dielectric layer having a thickness of T.sub.idl over:
said substrate;
said plurality of electrically unisolated;
and
said n electrically isolated metal lines;
wherein there is a separation S.sub.met between:
each electrically unisolated metal line and the nearest of one of:
another electrically unisolated metal line;
or
one of said electrically isolated metal lines;
each electrically isolated metal line and the nearest of one of:
another electrically isolated metal line;
or
one of said electrically unisolated metal lines;
wherein:
S.sub.met is not greater than or (1.4(n+1)T.sub.idl)+(n)W.sub.met) or twice T.sub.idl ;
n is a maximized whole number not greater than (S.sub.met -1.4T.sub.idl)/(1.4T.sub.idl +W.sub.met);
one of said plurality of electrically isolated or unisolated metal lines is diagonally spaced from the nearest portion of another one of said plurality of electrically isolated or unisolated metal lines by a distance that is equal to .sqroot.2* S.sub.met ;
and
said thickness of T.sub.idl has a value of at least (.sqroot.2*S.sub.met).div.2.

26 more elements

An integrated circuit structure comprising:

a substrate;
a plurality of electrically unisolated metal lines on said substrate each:
having the same height T.sub.MET and being parallel one with another;
and
being separated from the nearest of the other electrically unisolated metal lines;
n electrically isolated metal lines each:
having a width W.sub.met ;
and
being situated in the separation between the each electrically unisolated metal line and the nearest of the other electrically unisolated metal lines;
a dielectric layer having a thickness of T.sub.idl over:
said substrate;
said plurality of electrically unisolated;
and
said n electrically isolated metal lines;
a guard ring enclosing said plurality of electrically unisolated metal lines, a space being positioned between said guard ring and said plurality of electrically unisolated metal lines, said space having a maximum width that is less than or equal to about twice T.sub.idl ;
wherein there is a separation S.sub.met between:
each electrically unisolated metal line and the nearest of one of:
another electrically unisolated metal line;
or
one of said electrically isolated metal lines;
each electrically isolated metal line and the nearest of one of:
another electrically isolated metal line;
or
one of said electrically unisolated metal lines;
wherein:
S.sub.met is not greater than or (1.4(n+1)T.sub.idl)+(n)W.sub.met or twice T.sub.idl ;
n is a maximized whole number not greater than (S.sub.met -1.4T.sub.idl)/(1.4T.sub.idl +W.sub.met);
when the result of (S.sub.met -1.4T.sub.idl)/(1.4T.sub.idl +W.sub.met) is less than 1, then n is equal to zero;
when n is equal to zero, then one electrically unisolated metal line of said plurality of electrically unisolated metal lines has a first width and the nearest of said plurality of electrically unisolated metal lines has a second width;
said first width is different from said second width;
the distance between nearest portions on said electrically unisolated metal line having said first width and said electrically unisolated metal line having said second width is not less than S.sub.met.

28 more elements

Dependencies are inferred from the claim text.

Intermetal dielectric planarization by metal features layout modification

Life of this patent

Intermetal dielectric planarization by metal features layout modification

Life of this patent

Abstract

Claims22