Semiconductor device and a method of manufacture

A semiconductor device comprising:

• a semiconductor substrate;
• an impurity-doped region formed around the surface portion of said semiconductor substrate;
• a first insulating layer for defining at least one active region on said semiconductor substrate;
• a cell array region including a bit line formed on said first insulating layer, a second insulating layer for insulating said bit line, and a capacitor;
• said capacitor comprising a storage electrode formed on said second insulating layer and electrically connected with said impurity-doped region, a dielectric film formed on said storage electrode, and a plate electrode formed on said dielectric film;
• a peripheral circuit region formed adjacent said cell array region, with said second insulating layer extending into said peripheral circuit region wherein a step difference is defined by the respective surfaces of said cell array region and said peripheral circuit region;
• a dummy pattern formed on and covering substantially all of said peripheral circuit region thereby compensating for said step difference,said dummy pattern overlapping a portion of said plate electrode adjacent said peripheral circuit region;
• and
• a third insulating layer formed on said dummy pattern and over said cell array region, said third insulating layer being planarized.

A semiconductor device comprising:

• a semiconductor substrate;
• an impurity-doped region formed in the surface portion of said semiconductor substrate;
• a first insulating layer for defining at least one active region on said semiconductor substrate;
• a cell array region including a bit line formed on said first insulating layer, a second insulating layer for insulating said bit line, and a capacitor;
• said capacitor comprising a storage electrode formed on said second insulating layer and electrically connected with said impurity-doped region, a dielectric film formed on said storage electrode, and a plate electrode formed on said dielectric film;
• a peripheral circuit region formed adjacent said cell array region, with said second insulating layer extending into said peripheral circuit region;
• wherein said cell array region is formed in a recessed region of said semiconductor substrate relative to said peripheral circuit region, the respective surfaces of said cell array region and said peripheral circuit region defining a step difference;
• a dummy pattern for compensating for said step difference, said dummy pattern being formed on and covering substantially all of said peripheral circuit region and said dummy pattern overlapping a portion of said plate electrode adjacent said peripheral circuit region;
• and
• a third insulating layer formed on said dummy pattern and plate electrode of said cell array region, said third insulating layer being planarized.