Integrated two-tiered via-plug to improve metal lithography # 4

Abstract

A semiconductor structure is disclosed where the topography of the semiconductor substrate is improved by forming a two-tiered via. The two-tiered structure has a top portion and a bottom portion. PECVD-oxide is disposed in the top portion on top of a blanket metal layer formed in the bottom portion. The oxide layer in the top portions is planarized to a level such that all such structures are planar with respect to each other. In other words, the leveled surface thereover offers a uniformly flat depth-of-field which in turn makes possible the use of submicron opto-lithographic tools for the ultra high density integrated circuit chips. At a later process step, a tungsten via plug replaces the PECVD-oxide in the top portion, thus resulting in a two-tiered structure comprising a portion of the metal blanket metal in the bottom portion and the tungsten via-plug in the top portion. As a further improvement for the required flatness for submicron technologies, it is shown that silicon nitride may be introduced at a judiciously chosen process step so as to minimize the propagation of surface irregularities from one layer to another through minimizing the so-called microloading effect. The presence of silicon nitride along with another conformal oxide layer lining the two-tiered structure also serve the purposes of eliminating, what are called, the "exploding vias".

Dependencies are inferred from the claim text.