Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS
AssigneeAdvanced Micro Devices, Inc.
InventorsRobin W. Cheung, Mark S. Chang
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AssigneeAdvanced Micro Devices, Inc.
InventorsRobin W. Cheung, Mark S. Chang
Estimating the term…
The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
A semiconductor device formed on a wafer comprising source and drain regions contacted by source and drain contacts, respectively, and each source and drain region separated by a gate region contacted by a gate electrode, with a first level patterned interconnect contacting said source and drain contacts and said gate electrode in a desired pattern and with a second level patterned interconnect contacting said first level patterned interconnect by a plurality of metal lines, said metal lines separated by a first dielectric material, said second level patterned interconnect comprising a low resistance metal wherein said low resistance metal is selected from the group consisting of copper, gold, silver, and platinum and separated by a planarized dielectric material inert to diffusion of said low resistance metal.
Dependencies are inferred from the claim text.