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US 5,965,925 AGranted
Integrated circuit layout methods and layout structures
AssigneeArtisan Components, Inc.
InventorsSteve P. Kornachuk, Scott T. Becker
Life of this patent
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AssigneeArtisan Components, Inc.
InventorsSteve P. Kornachuk, Scott T. Becker
Estimating the term…
Disclosed is a semiconductor layout design for use in integrated circuits that use balance circuitry. The semiconductor layout design includes a set of four substantially self enclosing gate transistors being arranged symmetrically about a common point. Wherein, each of the set of four substantially self enclosing gate transistors have a gate width that is defined by a perimeter around each of the set of four substantially self enclosing gate transistors. The semiconductor layout design preferably includes a balanced circuit having a set of first transistors and a set of second transistors. The set of first transistors being wired diagonally across the set of four substantially self enclosing gate transistors. In a preferred embodiment, the set of second transistors are wired diagonally across the set of four substantially self enclosing gate transistors in a manner that ensures that the set of second transistors are wired substantially perpendicular to the set of first transistors.
A balanced circuitry layout, comprising:
A semiconductor layout as design;
A balanced circuit layout design;
Dependencies are inferred from the claim text.