Lateral bipolar transistor and apparatus using same

A lateral bipolar transistor, comprising:

• an emitter region formed in a well, wherein the emitter region has a first conductivity and
• the well has a second conductivity;
• a collector region formed in the well, wherein the collector region surrounds, and is laterally displaced from, the emitter region, further wherein the collector region has the first conductivity;
• a base region, wherein the base region is defined by a portion of the well interposed between the emitter region and the collector region;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region.

A lateral bipolar transistor, comprising:

• an emitter region;
• a collector region surrounding, and laterally displaced from, the emitter region;
• a base region interposed between the emitter region and the collector region, wherein an interface between the base region and the collector region forms a base-collector junction, further wherein an interface between the base region and the emitter region forms a base-emitter junction;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region, further wherein the gate region overlying at least a portion of the base region extends across the base-collector junction to overlie at least a portion of the collector region, still further wherein the gate region overlying at least a portion of the base region extends across the base-emitter junction to overlie at least a portion of the emitter region.

A lateral bipolar transistor, comprising:

• an emitter region;
• a collector region surrounding, and laterally displaced from, the emitter region;
• a base region interposed between the emitter region and the collector region;
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• and
• a metal oxide semiconductor inversion region underlying the gate region.

A lateral bipolar transistor, comprising:

• an emitter region formed in a retrograde well, wherein the emitter region has a first conductivity and the retrograde well has a second conductivity;
• a collector region formed in the retrograde well, wherein the collector region surrounds, and is laterally displaced from, the emitter region, further wherein the collector region has the first conductivity;
• a base region, wherein the base region is defined by a portion of the retrograde well interposed between the emitter region and the collector region;
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• and
• a metal oxide semiconductor inversion region underlying the gate region.

A system comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device comprises a lateral bipolar transistor, further wherein the lateral bipolar transistor comprises:
• an emitter region;
• a collector region surrounding, and laterally displaced from, the emitter region;
• a base region interposed between and adjacent the emitter region and the collector region;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region.

A system comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device comprises a lateral bipolar transistor, further wherein the lateral bipolar transistor comprises:
• an emitter region formed in a well, wherein the emitter region has a first conductivity and the well has a second conductivity;
• a collector region formed in the well, wherein the collector region surrounds, and is laterally displaced from, the emitter region, further wherein the collector region has the first conductivity;
• a base region, wherein the base region is defined by a portion of the well interposed between the emitter region and the collector region;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region.

A system comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device comprises a lateral bipolar transistor, further wherein the lateral bipolar transistor comprises:
• an emitter region;
• a collector region surrounding, and laterally displaced from, the emitter region;
• a base region interposed between the emitter region and the collector region, wherein an interface between the base region and the collector region forms a base-collector junction, further wherein an interface between the base region and the emitter region forms a base-emitter junction;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region, further wherein the gate region overlying at least a portion of the base region extends across the base-collector junction to overlie at least a portion of the collector region, still further wherein the gate region overlying at least a portion of the base region extends across the base-emitter junction to overlie at least a portion of the emitter region.

A system comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device comprises a lateral bipolar transistor, further wherein the lateral bipolar transistor comprises:
• an emitter region;
• a collector region surrounding, and laterally displaced from, the emitter region;
• a base region interposed between the emitter region and the collector region;
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• and
• a metal oxide semiconductor inversion region underlying the gate region.

A system comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device comprises a lateral bipolar transistor, further wherein the lateral bipolar transistor comprises:
• an emitter region formed in a retrograde well, wherein the emitter region has a first conductivity and the retrograde well has a second conductivity;
• a collector region formed in the retrograde well, wherein the collector region surrounds, and is laterally displaced from, the emitter region, further wherein the collector region has the first conductivity;
• a base region, wherein the base region is defined by a portion of the retrograde well interposed between the emitter region and the collector region;
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• and
• a metal oxide semiconductor inversion region underlying the gate region.

A lateral bipolar transistor, comprising:

• an emitter region;
• a collector region surrounding, and laterally displaced from, the emitter region;
• a base region interposed between the emitter region and the collector region;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• wherein angled implanting of dopants is used to selectively reduce the width of the base region.

A system comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device comprises a lateral bipolar transistor, further wherein the lateral bipolar transistor comprises:
• an emitter region;
• a collector region surrounding, and laterally displaced from, the emitter region;
• a base region interposed between the emitter region and the collector region;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• wherein angled implanting of dopants is used to selectively reduce the width of the base region.

A lateral bipolar transistor, comprising:

• an emitter region, wherein the emitter region has a first dopant type
• a collector region laterally displaced from the emitter region, wherein the collector region has a second dopant type, further wherein the second dopant type is opposite the first dopant type;
• a base region interposed between the emitter region and the collector region, wherein an interface between the base region and the emitter region forms a base-emitter junction, further wherein an interface between the base region and the collector region forms a base-collector junction;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• wherein a first implant of the first dopant type grades the base region at the base-emitter junction;
• and
• wherein a second implant of the second dopant type grades the base region at the base-collector junction.

A system comprising:

• a processor;
• and
• a memory device in communication with the processor, wherein the memory device comprises a lateral bipolar transistor, further wherein the lateral bipolar transistor comprises:
• an emitter region, wherein the emitter region has a first dopant type
• a collector region laterally displaced from the emitter region, wherein the collector region has a second dopant type, further wherein the second dopant type is opposite the first dopant type;
• a base region interposed between the emitter region and the collector region, wherein an interface between the base region and the emitter region forms a base-emitter junction, further wherein an interface between the base region and the collector region forms a base-collector junction;
• and
• a gate region overlying at least a portion of the base region, wherein the gate region is in electrical communication with the base region;
• wherein a first implant of the first dopant type grades the base region at the base-emitter junction;
• and
• wherein a second implant of the second dopant type grades the base region at the base-collector junction.