Semiconductor device including field effect transistor
AssigneeKabushiki Kaisha Toshiba
InventorMizuki Ono
Life of this patent
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Abstract
An insulating film having a low dielectric constant lower than that of silicon oxide is arranged between a silicon support layer and a silicon active layer. A channel region, source/drain regions, and a device isolation region are formed in the active layer. A gate electrode is arranged on the channel region through a gate insulating film. The active layer is covered with a TEOS film in which contact holes are formed. The contact holes are filled with wiring layers connected to the source/drain regions and the gate electrode.
Claims19
A semiconductor device including a field effect transistor, comprising:
- a support layer consisting essentially of silicon;
- a buried insulating layer arranged on said support layer;
- an active layer consisting essentially of silicon and arranged on said buried insulating layer, said buried insulating layer being interposed between said support layer and said active layer;
- source/drain regions and a channel region interposed therebetween, which are formed in said active layer to be in contact with said buried insulating layer;
- a gate electrode facing said channel region through an insulating film;
- and
- source/drain electrodes connected to said source/drain regions, respectively,
- wherein said buried insulating layer comprises a low-dielectric-constant region having a dielectric constant of from 1 to 3.9, along a route of lines of electric force extending from said channel region to each of said source/drain regions through said buried insulating layer to form a capacitive coupling between said channel region and each of said source/drain regions.
A semiconductor device including a field effect transistor, comprising:
- a support layer consisting essentially of silicon;
- a buried insulating layer arranged on said support layer and comprising a low-dielectric-constant region having a dielectric constant of from 1 to 3.9;
- an active layer consisting essentially of silicon and arranged on said buried insulating layer, said buried insulating layer being interposed between said support layer and said active layer;
- source/drain regions and a channel region interposed therebetween, which are formed in said active layer to be in contact with said buried insulating layer, said source/drain regions facing said low-dielectric-constant region;
- a gate electrode facing said channel region through an insulating film;
- and
- source/drain electrodes connected to said source/drain regions, respectively.
Dependencies are inferred from the claim text.