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AssigneeSanDisk Corporation
InventorsJack H. Yuan, Gheorghe Samachisa, Daniel C. Guterman, Eliyahou Harari
Estimating the term…
A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
An electrically programmable and erasable memory device formed on a semiconductor substrate, comprising an erase gate overlying the substrate, a floating gate partially overlapping the erase gate and a control gate overlying the floating gate, each of said gates including conductively doped polysilicon material, and a tunnel oxide layer between the erase and floating gates that is characterized by a conduction of electrons in a direction from the floating to the erase gate being higher than in an opposite direction.
An array of EEPROM cells formed on a semiconductor substrate, comprising:
Dependencies are inferred from the claim text.