Controlled linewidth reduction during gate pattern formation using a spin-on barc
AssigneeAdvanced Micro Devices, Inc.
InventorsChih-Yuh Yang, Scott A. Bell, Daniel Steckert
Life of this patent
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Abstract
A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.
Claims20
A method for forming a gate structure from a semiconductor wafer stack comprising a substrate and a conductive layer above the substrate, the method comprising:
- depositing an organic bottom anti-reflective coating (BARC) on the conductive layer;
- depositing a resist layer on the BARC;
- forming a first resist mask with the resist layer, wherein the first resist mask defines a first line having a first width;
- isotropically etching using a plasma comprised of HBr plus O.sub.2 the first resist mask to create a second mask, such that portions of the first line are removed to form a second line having a second width, wherein the second width is narrower than the first width;
- etching through selected portions of the gate conductive layer as defined by the second resist mask to form a gate from the gate conductive layer, wherein the gate has a gate width substantially equal to the second width.
A method for forming a gate on a semiconductor wafer using a bottom anti-reflective coating and a trim etch process, the method comprising:
- creating a wafer stack by forming a gate conductive layer over a substrate, depositing an organic bottom anti-reflective coating (BARC), and forming a resist mask on the BARC;
- isotropically etching using a plasma comprised of HBr plus O.sub.2 the resist mask and BARC to reduce a width of a gate line pattern formed in the resist mask;
- and shaping the wafer stack using the isotropically etched resist mask by etching through exposed portions of the gate conductive layer.
Dependencies are inferred from the claim text.