Method and apparatus for a high speed cyclical redundancy check system
AssigneeMicron Technology, Inc.
InventorsMark Thomann, Huy Thanh Vo, Charles L. Ingalls
Life of this patent
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Abstract
A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle.
Claims14
A method for cyclical redundancy check error generation in a bidirectional system having a cyclical redundancy check generator, a data latch, and a programmable data buffer connected by a plurality of data bus lines, the data latch having a precharge circuit and the data buffer having data buffer outputs programmable to support a plurality of error processing modes, the method comprising the steps of:
- inhibiting the cyclical redundancy check generator and the data buffer outputs;
- precharging the plurality of data bus lines to a first logic level until a cyclical redundancy check strobe is detected;
- turning off the precharge circuit;
- activating the data buffer outputs in accordance with one of the plurality of error processing modes corresponding to data stored within the data buffer to modulate charge on the plurality of data bus lines;
- waiting for a sufficient time for the plurality of data bus lines to develop a charge differential;
- latching data on the plurality of data bus lines in the data latch;
- and
- performing a cyclical redundancy check on the latched data wherein data transferred from the data buffer to a first data port is checked for errors and an error check word is generated for data transferred from the first data port to the data buffer.
A method for cyclical redundancy check error generation in a bidirectional system having a cyclical redundancy check generator, a data latch, and two programmable data buffers connected by a plurality of data bus lines, the data latch having a precharge circuit, and the data buffers having data outputs programmable to support a plurality of error processing modes, the method comprising the steps of:
- inhibiting the cyclical redundancy check generator and the data outputs;
- precharging the plurality of data bus lines to a first logic level until a cyclical redundancy check strobe is detected;
- turning off the precharge circuit;
- activating the data outputs from one of the data buffers in accordance with one of the plurality of error processing modes corresponding to data stored within the data buffer to modulate charge on the plurality of data bus lines;
- waiting for a sufficient time for the plurality of data bus lines to develop a charge differential;
- latching data on the plurality of data bus lines in the data latch;
- and
- performing a cyclical redundancy check on the latched data wherein data transferred from the data buffer to a first data port is checked for errors and an error check word is generated for data transferred from the first data port to the data buffer.
A bidirectional programmable error detection and correction system comprising:
- an edit buffer programmable to support a plurality of error processing modes;
- an error check module programmable for generating and comparing error check words;
- a first parallel data bus programmable for transferring data from the edit buffer to a first data port;
- a second parallel data bus programmable for transferring data from the first data port to the error check module and to the edit buffer, and further programmable for transferring data from the edit buffer to the error check module;
- a third parallel data bus programmable for transferring an error check word between the error check module and the edit buffer;
- a control module for programming the first, second and third data buses, and the error check module to operate according to the plurality of error processing modes, wherein data transferred from the edit buffer to the first data port is checked for errors and an error check work is generated for data transferred from the first data port to the edit buffer.
Dependencies are inferred from the claim text.