VRAM-based parity engine for use in disk array controller

A video random access memory based parity engine connected to a PCI bus interface and a disk cache memory, said parity engine comprising:

• a video memory;
• a direct memory access controller connected to said PCI bus interface for providing control signals to DRAM controller, VRAM controller XOR logic and buffers in order to controll transmission and receipt of data between said disk cache memory and said video memory, and for providing control signals to DRAM controller, VRAM controller XOR logic and buffers in order to get parity data;
• a video memory controller for receiving the control signals from said direct memory access controller to transmit data from said disk cache memory to said video memory and generating control signal for operating said video memory;
• an arithmetic logic means for calculating old parity data of said video memory and new parity data of said disk cache memory under control of said direct memory access controller, wherein said video memory temporarily stores the new parity data in accordance with the control signals from said video memory controller;
• and
• a transmitting/receiving means for transmitting and receiving data from said disk cache memory, the new parity data from said arithmetic logic means, said video memory and said PCI bus interface.