US 5,964,883 A · Arrangement and method for handling bus clock speed variations

Abstract

An arrangement for monitoring clock frequency variations on a peripheral bus is provided to improve operations of the peripheral device despite changes in the clock frequency. In one aspect of the arrangement, a processing unit is coupled to a host bus which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating a different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.

Claims17

Dependent claims

A system comprising:

a host bus;
a host processing unit coupled to the host bus;
a peripheral bus coupled to the host bus;
a peripheral device coupled to the peripheral bus;
and
a frequency monitoring unit configured and arranged to detect a frequency variation between a clock frequency of the peripheral bus at two different times during operation of the host processing unit, which exceeds a change threshold associated with the peripheral device and to generate a frequency change indication which indicates that the clock frequency of the peripheral bus has changed by an amount which exceeds the change threshold.

3 more elements

A method of controlling system operation in a system having a processing unit coupled to a host bus and a peripheral device coupled to a peripheral bus, the peripheral bus being coupled to the host bus, the method comprising:

detecting a frequency variation in the clock frequency of the peripheral bus at two different times during operation of the processing unit;
determining if the frequency variation exceeds a predetermined change threshold associated with the peripheral device;
and
in response to the frequency variation exceeding the predetermined change threshold, informing the peripheral device that the clock frequency of the peripheral bus has changed by an amount which exceeds the change threshold.

1 more element

Dependencies are inferred from the claim text.

Arrangement and method for handling bus clock speed variations

Life of this patent

Arrangement and method for handling bus clock speed variations

Life of this patent

Abstract

Claims17