Multiple timer architecture with pipelining
AssigneeAdvanced Micro Devices, Inc.
InventorShankar Dey
Life of this patent
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Abstract
A timer counter with multiple timers in a pipelined architecture in which the multiple timers are serviced in the pipeline. The timer counter includes a control unit having a first control section and a second control section for sequencing the servicing of each of the multiple timers in a pipeline. The first and second control sections provide a pipeline sequence of the total required service of the timer counter. The pipeline architecture allows the multiple timers to be serviced in a pipeline without increasing the overall number of clocks.
Claims5
A pipelined counter timer for a computer system, comprising:
- multiple timers each having an associated counter register and an output;
- a first multiplexor for multiplexing the outputs from the multiple timers and associated counter registers;
- a counter element receiving the multiplexed output from the first multiplexor;
- multiple timer control registers each having an output;
- a second multiplexor for multiplexing the outputs from the timer control registers;
- first and second controls for receiving the multiplexed output from the second multiplexor, wherein the first and second controls provide first and second servicing sequences and wherein the first control has an output to the counter element;
- a third multiplexor for multiplexing an output from the counter element and a ground signal;
- a comparator receiving inputs from the counter element and from the second control and an output to the third multiplexor;
- and
- a demultiplexor for demultiplexing an output from the third multiplexor and for providing demultiplexed signals to the multiple timers and associated counter registers.
A method of pipeline servicing multiple timers in a timer counter for a computer system, the method comprising:
- multiplexing outputs from multiple timers and associated counter registers;
- inputting the multiplexed outputs from the multiple timers and associated counter registers into a counter element;
- multiplexing outputs from multiple timer control registers;
- generating first and second servicing sequences in first and second controls which receive the multiplexed outputs from the multiple timer control registers;
- inputting the first and second servicing sequences to the counter element;
- inputting the first and second servicing sequences to the multiple timers and associated counter registers;
- and
- inputting a signal from the second control to a comparator.
Dependencies are inferred from the claim text.